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| fme-mb96350 rev 7 fujitsu semiconductor data sheet copyright ?2010 fujitsu semiconductor limited all rights reserved 2010.6 for the information for microcontroller supports, see the following web site. this web site includes the "customer design review supplement" which provides the latest cautions on system development and the minimal requirements to be checked to prevent problems before the system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc-16fx mb96350 series MB96F353/f355 mb96f356 description mb96350 series is based on fujitsu s advanced 16fx architecture (16-bit with instruction pipeline for risc-like performance). the cpu uses the same instruction set as the established 16lx series - thus allowing for easy migration of 16lx software to the new 16fx products. 16fx improvements compared to the previous generation include signi?antly improved performance - even at the same operation frequency, reduced power consumption and faster start-up time. for highest processing speed at optimized power consumption an internal pll can be selected to supply the cpu with up to 56mhz operation frequency from an external 4mhz resonator. the result is a minimum instruction cycle time of 17.8ns going together with excellent emi behavior. an on-chip clock modulation circuit signi?antly reduces emission peaks in the frequency spectrum. the emitted power is minimized by the on-chip voltage regulator that reduces the internal cpu voltage. a ?xible clock tree allows to select suitable operation frequencies for peripheral resources independent of the cpu speed. note: f 2 mc is the abbreviation of fujitsu flexible microcontroller www.datasheet.in
mb96350 series 2 fme-mb96350 rev 7 features feature description technology 0.18 m cmos cpu ? 2 mc-16fx cpu up to 56 mhz internal, 17.8 ns instruction cycle time optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) 8-byte instruction execution queue signed multiply (16-bit 16-bit) and divide (32-bit/16-bit) instructions available system clock on-chip pll clock multiplier (x1 - x25, x1 when pll stop) 3 mhz - 16 mhz external crystal oscillator clock (maximum frequency when using ceramic resonator depends on q-factor). up to 56 mhz external clock 32-100 khz subsystem quartz clock 100khz/2mhz internal rc clock for quick and safe startup, oscillator stop detection, watchdog clock source selectable from main- and subclock oscillator (part number suffix ?? and on-chip rc oscillator, independently for cpu and 2 clock domains of peripherals. low power consumption - 13 operating modes : (different run, sleep, timer modes, stop mode) clock modulator on-chip voltage regula- tor internal voltage regulator supports reduced internal mcu voltage, offering low emi and low power consumption figures low voltage reset reset is generated when supply voltage is below minimum. code security protects rom content from unintended read-out memory patch function replaces rom content can also be used to implement embedded debug support dma automatic transfer function independent of cpu, can be assigned freely to resources interrupts fast interrupt processing 8 programmable priority levels non-maskable interrupt (nmi) timers three independent clock timers (23-bit rc clock timer, 23-bit main clock timer, 17-bit sub clock timer) watchdog timer www.datasheet.in mb96350 series fme-mb96350 rev 7 3 can supports can protocol version 2.0 part a and b iso16845 certified bit rates up to 1 mbit/s 32 message objects each message object has its own identifier mask programmable fifo mode (concatenation of message objects) maskable interrupt disabled automatic retransmission mode for time triggered can applications programmable loop-back mode for self-test operation usart full duplex usarts (sci/lin) wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c up to 400 kbps master and slave functionality, 7-bit and 10-bit addressing a/d converter sar-type 10-bit resolution signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger or reload timer reload timers 16-bit wide prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency event count function free running timers signals an interrupt on overflow, supports timer clear upon match with output compare (0, 4), prescaler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 ,1/2 8 of peripheral clock frequency input capture units 16-bit wide signals an interrupt upon external event rising edge, falling edge or rising & falling edge sensitive output compare units 16-bit wide signals an interrupt when a match with 16-bit i/o timer occurs a pair of compare registers can be used to generate an output signal. programmable pulse generator 16-bit down counter, cycle and duty setting registers interrupt at trigger, counter borrow and/or duty match pwm operation and one-shot operation internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock and reload timer underflow as clock input can be triggered by software or reload timer feature description www.datasheet.in mb96350 series 4 fme-mb96350 rev 7 real time clock can be clocked either from sub oscillator (devices with part number suffix ??, main oscillator or from the rc oscillator facility to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) read/write accessible second/minute/hour registers can signal interrupts every half second/second/minute/hour/day internal clock divider and prescaler provide exact 1s clock external interrupts edge sensitive or level sensitive interrupt mask and pending bit per channel each available can channel rx has an external interrupt for wake-up selected usart channels sin have an external interrupt for wake-up non maskable interrupt disabled after reset once enabled, can not be disabled other than by reset. level high or level low sensitive pin shared with external interrupt 0. external bus interface 8-bit or 16-bit bidirectional data up to 24-bit addresses 6 chip select signals multiplexed address/data lines wait state request external bus master possible timing programmable i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs (except when used as i2c sda/scl line) bit-wise programmable as input/output or peripheral signal bit-wise programmable input enable bit-wise programmable input levels: automotive / cmos-schmitt trigger / ttl bit-wise programmable pull-up resistor bit-wise programmable output driving strength for emi optimization packages 64-pin plastic lqfp m23/m24 feature description www.datasheet.in mb96350 series fme-mb96350 rev 7 5 flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycles: 10,000 times data retention time: 20 years erase can be performed on each sector individually sector protection flash security feature to protect the content of the flash low voltage detection during flash erase feature description www.datasheet.in mb96350 series 6 fme-mb96350 rev 7 product lineup features mb96v300b mb96(f)35x product type evaluation sample flash product: mb96f35x mask rom product: mb9635x product options ys na low voltage reset persistently on / single clock devices rs low voltage reset can be disabled / single clock devices yw low voltage reset persistently on / dual clock devices rw low voltage reset can be disabled / dual clock devices as no can / low voltage reset can be disabled / single clock devices aw no can / low voltage reset can be disabled / dual clock devices flash/ rom ram 96kb 8kb rom/flash memory emulation by external ram, 92kb internal ram MB96F353r, MB96F353a 160kb 8kb mb96f355r, mb96f355a 288kb 12kb mb96f356y, mb96f356r, mb96f356a package bga416 fpt-64p-m23/24 dma 16 channels 4 channels usart 10 channels 4 channels i2c 2 channels 1 channel a/d converter 40 channels 15 channels a/d converter reference voltage switch yes no 16-bit reload timer 6 channels + 1 channel (for ppg) 4 channels + 1 channel (for ppg) 16-bit free-running timer 4 channels 4 channels (2 channels with external clock input pin) 16-bit output compare 12 channels 4 channels 16-bit input capture 12 channels 6 channels (plus 2 channels for lin usart) 16-bit programmable pulse generator 20 channels 20 channels can interface 5 channels mb96f35xa: no MB96F353r/f355r: 1 channel mb96f356y/r: 2 channels external interrupts 16 channels 13 channels non-maskable interrupt 1 channel www.datasheet.in mb96350 series fme-mb96350 rev 7 7 real time clock 1 i/o ports 136 49 for part number with suf? "w", 51 for part number with suf? "s" external bus interface yes chip select 6 signals clock output function 2 channels low voltage reset yes on-chip rc-oscillator yes features mb96v300b mb96(f)35x www.datasheet.in mb96350 series 8 fme-mb96350 rev 7 block diagram block diagram of mb96(f)35x i2c 1 ch. sda0 scl0 dma controller boot rom peripheral bus bridge peripheral bus bridge 16fx core bus (clkb) usart 4 ch. 10-bit adc 15 ch. i/o timer 0 icu 0/1 can interface 2 ch. real time clock watchdog ram voltage regulator sin2, sin2_r, sin3, sin7_r, sin8_r sot2, sot2_r, sot3, sot7_r, sot8_r sck2, sck2_r, sck3, sck7_r, sck8_r wot av cc av ss avrh an0 ... an14 adtg_r frck0 in0 ... in1 out4 ... out7 tx1 *2 , tx2 *3 rx1 *2 , rx2 *3 peripheral bus 1 (clkp1) peripheral bus 2 (clkp2) v cc v ss c i/o timer 1 icu 4/5/6/7 frck1 in4 ... in7 16fx cpu interrupt controller clock & mode controller flash memory a memory patch unit ad00 ... ad15 a16 ... a21 ale rdx wr(l)x, wrhx hrq hakx rdy eclk external bus interface cs0_r ... cs5_r nmi_r ocu 4/5/6/7 16-bit reload timer 4 ch. tin0_r, tin2_r tin1, tin3 tot0_r, tot2_r tot1, tot3 external interrupt int8 ... int15 int0_r, int2_r, int4_r int3_r1 int7_r, int9_r ... int11_r 16-bit ppg 20 ch. ppg0 ... ppg7, ppg12 ... ppg15 ttg0, ttg1, ttg4 ... ttg9, ttg12 ... ttg15 ppg8_r ... ppg11_r, ppg16_r ... ppg19_r ttg8_r ... ttg11_r, ttg16_r ... ttg19_r ckot0_r, ckot1, ckot1_r ckotx1 x0, x1 x0a, x1a *1 rstx md0...md2 rlt6 *1: x0a, x1a only available on devices with suf? ? *2: tx1, rx1 only available on mb96f356y/r i/o timer 2 icu 9 i/o timer 3 icu 10 *3: tx2, rx2 only available on mb96f356y/r and MB96F353r/f355r www.datasheet.in mb96350 series fme-mb96350 rev 7 9 pin assignments pin assignment of mb96(f)35x remark: mb96(f)35x products are pin-compatible to f 2 mc-16lx family mb90350 series. lqfp - 64 package code (mold) fpt-64p-m23/m24 (fpt-64p-m23/m24) p00_1/ad01/int9/sot7_r/ttg9_r p00_2/ad02/int10/sin7_r/ttg10_r p00_3/ad03/int11/sck8_r/ttg11_r p00_4/ad04/int12/sot8_r/ppg8_r p00_5/ad05/int13/sin8_r/ppg9_r p00_6/ad06/int14/ppg10_r p00_7/ad07/int15/ppg11_r p01_0/ad08/ckot1/tin1/ttg16_r p01_1/ad09/ckotx1/tot1/ttg17_r p01_2/ad10/int11_r/sin3/ttg18_r p01_3/ad11/sot3/ttg19_r p01_4/ad12/sck3/ppg16_r p01_5/ad13/sin2_r/int7_r/ppg17_r p01_6/ad14/sot2_r/ppg18_r p01_7/ad15/sck2_r/ppg19_r p02_0/a16/ppg12/ckot1_r p02_1/a17/ppg13 p02_2/a18/ppg14/ckot0_r p02_3/a19/ppg15 p02_4/a20/ttg8/ttg0/in0 p02_5/a21/ttg9/ttg1/in1/adtg_r vcc vss x1 x0 md1 md2 p06_7/an7/ppg7 p06_6/an6/ppg6 p06_5/an5/ppg5/cs5_r p06_4/an4/ppg4/cs4_r p06_3/an3/ppg3/cs3_r p06_2/an2/ppg2/cs2_r p06_1/an1/ppg1/cs1_r p06_0/an0/ppg0/cs0_r avss avrh avcc p05_6/an14/int4_r p05_5/an13/int0_r/nmi_r p05_4/an12/tot3/int2_r p00_0/ad00/int8/sck7_r/ttg8_r rstx md0 p03_0/ale/in4/ttg4/ttg12/tot0_r p03_1/rdx/in5/ttg5/ttg13/tot2_r p03_2/wr(l)x/rx2/int10_r *3 p03_3/tx2/wrhx *3 p03_4/hrq/out4 p03_5/hakx/out5 p03_6/rdy/out6 p03_7/eclk/out7 x0a/p04_0 *1 x1a/p04_1 *1 vss c p04_2/in6/rx1/int9_r/ttg6/ttg14 *2 p04_3/in7/tx1/ttg7/ttg15 *2 p04_4/sda0/frck0/tin0_r p04_5/scl0/frck1/tin2_r p05_0/an8/sin2/int3_r1 p05_1/an9/sot2 p05_2/an10/sck2 p05_3/an11/tin3/wot 89 12345 7 6 10111213141516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 devices with suf? w: x0a, x1a devices with suf? s: p04_0, p04_1 *1: *2: tx1, rx1 only available on mb96f356y/r *3: tx2, rx2 only available on mb96f356y/r and MB96F353r/f355r www.datasheet.in mb96350 series 10 fme-mb96350 rev 7 pin function description pin function description (1 of 2) pin name feature description adn external bus external bus interface (multiplexed mode) address output and data input/output adtg_r adc relocated a/d converter trigger input ale external bus external bus address latch enable output an external bus external bus address output ann adc a/d converter channel n input av cc supply analog circuits power supply avrh adc a/d converter high reference voltage input av ss supply analog circuits power supply c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output ckotn_r clock output function relocated clock output function n output ckotxn clock output function clock output function n inverted output eclk external bus external bus clock output csn_r external bus relocated external bus chip select n output frckn free running timer free running timer n input hakx external bus external bus hold acknowledge hrq external bus external bus hold request inn icu input capture unit n input intn external interrupt external interrupt n input intn_r external interrupt relocated external interrupt n input mdn core input pins for specifying the operating mode. nmi_r external interrupt relocated non-maskable interrupt input outn ocu output compare unit n waveform output pxx_n gpio general purpose io ppgn ppg programmable pulse generator n output ppgn_r ppg relocated programmable pulse generator n output rdx external bus external bus interface read strobe output rdy external bus external bus interface external wait state request input www.datasheet.in mb96350 series fme-mb96350 rev 7 11 rstx core reset input rxn can can interface n rx input sckn usart usart n serial clock input/output sckn_r usart relocated usart n serial clock input/output scln i2c i2c interface n clock i/o input/output sdan i2c i2c interface n serial data i/o input/output sinn usart usart n serial data input sinn_r usart relocated usart n serial data input sotn usart usart n serial data output sotn_r usart relocated usart n serial data output tinn reload timer reload timer n event input tinn_r reload timer relocated reload timer n event input totn reload timer reload timer n output totn_r reload timer relocated reload timer n output ttgn ppg programmable pulse generator n trigger input ttgn_r ppg relocated programmable pulse generator n trigger input txn can can interface n tx output v cc supply power supply v ss supply power supply wot rtc real timer clock output wrhx external bus external bus high byte write strobe output wrlx/wrx external bus external bus low byte / word write strobe output x0 clock oscillator input x0a clock subclock oscillator input (only for devices with suf? "w") x1 clock oscillator output x1a clock subclock oscillator output (only for devices with suf? "w") pin function description (2 of 2) pin name feature description www.datasheet.in mb96350 series 12 fme-mb96350 rev 7 pin circuit type *1: please refer to i/o circuit type?for details on the i/o circuit types *2: devices with suf? ? *3: devices without suf? ? pin circuit types fpt-64p-m23/24 pin no. circuit type *1 1 supply 2g 3 to 15 i 16,17 h 18 supply 19,20 b *2 19,20 h *3 21 to 23 c 24 to 44 h 45 e 46,47 a 48,49 supply 50 f 51 h 52,53 n 54 to 61 h 62,63 i 64 supply www.datasheet.in mb96350 series fme-mb96350 rev 7 13 i/o circuit type type circuit remarks a high-speed oscillation circuit: programmable between oscillation mode (ex- ternal crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x0 pin) programmable feedback resistor = approx. 2 * 0.5 m ? . feedback resistor is grounded in the center when the oscillator is disabled or in fci mode b low-speed oscillation circuit: programmable feedback resistor = approx. 2*5m ? . feedback resistor is grounded in the center when the oscillator is disabled c mask rom and eva device: cmos hysteresis input pin flash device: cmos input pin e cmos hysteresis input pin pull-up resistor value: approx. 50 k ? x1 x0 r r mrfbe xout fci 0 1 fci or osc disable x1a x0a r r srfbe xout osc disable r hysteresis inputs r pull-up resistor hysteresis inputs www.datasheet.in mb96350 series 14 fme-mb96350 rev 7 f power supply input protection circuit g a/d converter ref+ (avrh) power supply input pin with protection circuit flash devices do not have a protection circuit against vcc for pin avrh h cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. note: MB96F353/f355: only automotive input and cmos hyster- esis input (0.7/0.3) are supported type circuit remarks ane avr ane pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown www.datasheet.in mb96350 series fme-mb96350 rev 7 15 i cmos level output (programmable i ol =5ma, i oh = -5ma and i ol = 2ma, i oh = -2ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function. programmable pull-up resistor: 50k ? approx. analog input note: MB96F353/f355: only automotive input and cmos hyster- esis input (0.7/0.3) are supported n cmos level output (i ol = 3ma, i oh = -3ma) 2 different cmos hysteresis inputs with input shutdown function automotive input with input shutdown function ttl input with input shutdown function programmable pull-up resistor: 50k ? approx. *1: n-channel transistor has slew rate control ac- cording to i 2 c spec, irrespective of usage note: MB96F353/f355: only automotive input and cmos hyster- esis input (0.7/0.3) are supported type circuit remarks r hysteresis input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown pull-up control pout nout automotive input ttl input analog input pout pull-up control nout r hysteresis input automotive input ttl input hysteresis input standby control for input shutdown standby control for input shutdown standby control for input shutdown standby control for input shutdown www.datasheet.in mb96350 series 16 fme-mb96350 rev 7 memory map mb96v300b mb96(f)35x ff:ffff h emulation rom user rom / external bus *4 de:0000 h external bus external bus 10:0000 h 0f:e000 h boot-rom boot-rom reserved reserved 0e:0000 h external ram 02:0000 h internal ram bank 1 reserved ramend1 *2 internal ram bank 1 ram availability de- pending on the device ramstart1 2 01:0000 h reserved rom/ram mirror rom/ram mirror 00:8000 h internal ram bank 0 internal ram bank 0 ramstart0 *2 reserved ramstart0 *3 external bus external bus end address *2 00:0c00 h external bus peripherals peripherals 00:0380 h 00:0180 h gpr *1 gpr *1 00:0100 h dma dma 00:00f0 h external bus external bus 00:0000 h peripheral peripheral *1: unused gpr banks can be used as ram area *2: for external bus end address and ramstart/end addresses, please refer to the table on the next page. *3: for eva device, ramstart0 depends on the con?uration of the emulated device. *4: for details about user rom area, see the user rom memory map for flash devices on the following pages. the external bus area and dma area are only available if the device contains the corresponding resource. the available ram and rom area depends on the device. www.datasheet.in mb96350 series fme-mb96350 rev 7 17 ramstart/end and external bus end addresses devices bank 0 ram size bank 1 ram size external bus end address ramstart0 ramstart1 ramend1 MB96F353/f355 8kbyte - 00:51ff h 00:6240 h -- mb96f356 12kbyte - 00:51ff h 00:5240 h -- www.datasheet.in mb96350 series 18 fme-mb96350 rev 7 user rom memory map for flash devices MB96F353 mb96f355 mb96f356 alternative mode cpu address flash memory mode address flash size 96kbyte flash size 160kbyte flash size 288kbyte ff:ffff h ff:0000 h 3f:ffff h 3f:0000 h s39 - 64k s39 - 64k s39 - 64k flash a fe:ffff h fe:0000 h 3e:ffff h 3e:0000 h external bus s38 - 64k s38 - 64k fd:ffff h fd:0000 h 3d:ffff h 3d:0000 h external bus s37 - 64k fc:ffff h fc:0000 h 3c:ffff h 3c:0000 h s36 - 64k fb:ffff h fb:0000 h 3b:ffff h 3b:0000 h external bus fa:ffff h fa:0000 h 3a:ffff h 3a:0000 h f9:ffff h f9:0000 h 39:ffff h 39:0000 h f8:ffff h f8:0000 h 38:ffff h 38:0000 h f7:ffff h f7:0000 h 37:ffff h 37:0000 h f6:ffff h f6:0000 h 36:ffff h 36:0000 h f5:ffff h f5:0000 h 35:ffff h 35:0000 h f4:ffff h f4:0000 h 34:ffff h 34:0000 h f3:ffff h f3:0000 h 33:ffff h 33:0000 h f2:ffff h f2:0000 h 32:ffff h 32:0000 h f1:ffff h f1:0000 h 31:ffff h 31:0000 h f0:ffff h f0:0000 h 30:ffff h 30:0000 h e0:ffff h e0:0000 h df:ffff h df:8000 h reserved reserved reserved df:7fff h df:6000 h 1f:7fff h 1f:6000 h sa3 - 8k sa3 - 8k sa3 - 8k flash a df:5fff h df:4000 h 1f:5fff h 1f:4000 h sa2 - 8k sa2 - 8k sa2 - 8k df:3fff h df:2000 h 1f:3fff h 1f:2000 h sa1 - 8k sa1 - 8k sa1 - 8k df:1fff h df:0000 h 1f:1fff h 1f:0000 h sa0 - 8k *1 sa0 - 8k *1 sa0 - 8k *1 de:ffff h de:0000 h reserved reserved reserved *1: sector sa0 contains the rom con?uration block rcba at cpu address df:0000 h - df:007f h www.datasheet.in mb96350 series fme-mb96350 rev 7 19 serial programming communication interface note: if a flash programmer and its software needs to use a handshaking pin, fujitsu suggests to the tool vendor to support at least port p00_1 on pin 25. if handshaking is used by the tool but p00_1 is not available in customer s application, fujitsu suggests to the customer to check the tool manual or to contact the tool vendor for alternative handshaking pins. usart pins for flash serial programming (md[2:0] = 010) mb96f35x pin number usart number normal function lqfp-64 9 usart2 sin2 10 sot2 11 sck2 34 usart3 sin3 35 sot3 36 sck3 26 usart7 sin7_r 25 sot7_r 24 sck7_r 29 usart8 sin8_r 28 sot8_r 27 sck8_r www.datasheet.in mb96350 series 20 fme-mb96350 rev 7 i/o map i/o map mb96(f)35x (1 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access 000000 h i/o port p00 - port data register pdr00 r/w 000001 h i/o port p01 - port data register pdr01 r/w 000002 h i/o port p02 - port data register pdr02 r/w 000003 h i/o port p03 - port data register pdr03 r/w 000004 h i/o port p04 - port data register pdr04 r/w 000005 h i/o port p05 - port data register pdr05 r/w 000006 h i/o port p06 - port data register pdr06 r/w 000007 h - 000017 h reserved - 000018 h adc0 - control status register low adcsl adcs r/w 000019 h adc0 - control status register high adcsh r/w 00001a h adc0 - data register low adcrl adcr r 00001b h adc0 - data register high adcrh r 00001c h adc0 - setting register adsr r/w 00001d h adc0 - setting register r/w 00001e h adc0 - extended con?uration register adecr r/w 00001f h reserved - 000020 h frt0 - data register of free-running timer tcdt0 r/w 000021 h frt0 - data register of free-running timer r/w 000022 h frt0 - control status register of free-running timer low tccsl0 tccs0 r/w 000023 h frt0 - control status register of free-running timer high tccsh0 r/w 000024 h frt1 - data register of free-running timer tcdt1 r/w 000025 h frt1 - data register of free-running timer r/w 000026 h frt1 - control status register of free-running timer low tccsl1 tccs1 r/w 000027 h frt1 - control status register of free-running timer high tccsh1 r/w 000028 h - 000033 h reserved - www.datasheet.in mb96350 series fme-mb96350 rev 7 21 000034 h ocu4 - output compare control status ocs4 r/w 000035 h ocu5 - output compare control status ocs5 r/w 000036 h ocu4 - compare register occp4 r/w 000037 h ocu4 - compare register r/w 000038 h ocu5 - compare register occp5 r/w 000039 h ocu5 - compare register r/w 00003a h ocu6 - output compare control status ocs6 r/w 00003b h ocu7 - output compare control status ocs7 r/w 00003c h ocu6 - compare register occp6 r/w 00003d h ocu6 - compare register r/w 00003e h ocu7 - compare register occp7 r/w 00003f h ocu7 - compare register r/w 000040 h icu0/icu1 - control status register ics01 r/w 000041 h icu0/icu1 - edge register ice01 r/w 000042 h icu0 - capture register low ipcpl0 ipcp0 r 000043 h icu0 - capture register high ipcph0 r 000044 h icu1 - capture register low ipcpl1 ipcp1 r 000045 h icu1 - capture register high ipcph1 r 000046 h - 00004b h reserved 00004c h icu4/icu5 - control status register ics45 r/w 00004d h icu4/icu5 - edge register ice45 r/w 00004e h icu4 - capture register low ipcpl4 ipcp4 r 00004f h icu4 - capture register high ipcph4 r 000050 h icu5 - capture register low ipcpl5 ipcp5 r 000051 h icu5 - capture register high ipcph5 r 000052 h icu6/icu7 - control status register ics67 r/w 000053 h icu6/icu7 - edge register ice67 r/w 000054 h icu6 - capture register low ipcpl6 ipcp6 r 000055 h icu6 - capture register high ipcph6 r i/o map mb96(f)35x (2 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 22 fme-mb96350 rev 7 000056 h icu7 - capture register low ipcpl7 ipcp7 r 000057 h icu7 - capture register high ipcph7 r 000058 h extint0 - external interrupt enable register enir0 r/w 000059 h extint0 - external interrupt interrupt request reg- ister eirr0 r/w 00005a h extint0 - external interrupt level select low elvrl0 elvr0 r/w 00005b h extint0 - external interrupt level select high elvrh0 r/w 00005c h extint1 - external interrupt enable register enir1 r/w 00005d h extint1 - external interrupt interrupt request reg- ister eirr1 r/w 00005e h extint1 - external interrupt level select low elvrl1 elvr1 r/w 00005f h extint1 - external interrupt level select high elvrh1 r/w 000060 h rlt0 - timer control status register low tmcsrl0 tmcsr0 r/w 000061 h rlt0 - timer control status register high tmcsrh0 r/w 000062 h rlt0 - reload register - for writing tmrlr0 w 000062 h rlt0 - reload register - for reading tmr0 r 000063 h rlt0 - reload register - for writing w 000063 h rlt0 - reload register - for reading r 000064 h rlt1 - timer control status register low tmcsrl1 tmcsr1 r/w 000065 h rlt1 - timer control status register high tmcsrh1 r/w 000066 h rlt1 - reload register - for writing tmrlr1 w 000066 h rlt1 - reload register - for reading tmr1 r 000067 h rlt1 - reload register - for writing w 000067 h rlt1 - reload register - for reading r 000068 h rlt2 - timer control status register low tmcsrl2 tmcsr2 r/w 000069 h rlt2 - timer control status register high tmcsrh2 r/w 00006a h rlt2 - reload register - for writing tmrlr2 w 00006a h rlt2 - reload register - for reading tmr2 r 00006b h rlt2 - reload register - for writing w 00006b h rlt2 - reload register - for reading r 00006c h rlt3 - timer control status register low tmcsrl3 tmcsr3 r/w i/o map mb96(f)35x (3 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 23 00006d h rlt3 - timer control status register high tmcsrh3 r/w 00006e h rlt3 - reload register - for writing tmrlr3 w 00006e h rlt3 - reload register - for reading tmr3 r 00006f h rlt3 - reload register - for writing w 00006f h rlt3 - reload register - for reading r 000070 h rlt6 - timer control status register low (dedic. rlt for ppg) tmcsrl6 tmcsr6 r/w 000071 h rlt6 - timer control status register high (dedic. rlt for ppg) tmcsrh6 r/w 000072 h rlt6 - reload register (dedic. rlt for ppg) - for writing tmrlr6 w 000072 h rlt6 - reload register (dedic. rlt for ppg) - for reading tmr6 r 000073 h rlt6 - reload register (dedic. rlt for ppg) - for writing w 000073 h rlt6 - reload register (dedic. rlt for ppg) - for reading r 000074 h ppg3-ppg0 - general control register 1 low gcn1l0 gcn10 r/w 000075 h ppg3-ppg0 - general control register 1 high gcn1h0 r/w 000076 h ppg3-ppg0 - general control register 2 low gcn2l0 gcn20 r/w 000077 h ppg3-ppg0 - general control register 2 high gcn2h0 r/w 000078 h ppg0 - timer register ptmr0 r 000079 h ppg0 - timer register r 00007a h ppg0 - period setting register pcsr0 w 00007b h ppg0 - period setting register w 00007c h ppg0 - duty cycle register pdut0 w 00007d h ppg0 - duty cycle register w 00007e h ppg0 - control status register low pcnl0 pcn0 r/w 00007f h ppg0 - control status register high pcnh0 r/w 000080 h ppg1 - timer register ptmr1 r 000081 h ppg1 - timer register r 000082 h ppg1 - period setting register pcsr1 w i/o map mb96(f)35x (4 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 24 fme-mb96350 rev 7 000083 h ppg1 - period setting register w 000084 h ppg1 - duty cycle register pdut1 w 000085 h ppg1 - duty cycle register w 000086 h ppg1 - control status register low pcnl1 pcn1 r/w 000087 h ppg1 - control status register high pcnh1 r/w 000088 h ppg2 - timer register ptmr2 r 000089 h ppg2 - timer register r 00008a h ppg2 - period setting register pcsr2 w 00008b h ppg2 - period setting register w 00008c h ppg2 - duty cycle register pdut2 w 00008d h ppg2 - duty cycle register w 00008e h ppg2 - control status register low pcnl2 pcn2 r/w 00008f h ppg2 - control status register high pcnh2 r/w 000090 h ppg3 - timer register ptmr3 r 000091 h ppg3 - timer register r 000092 h ppg3 - period setting register pcsr3 w 000093 h ppg3 - period setting register w 000094 h ppg3 - duty cycle register pdut3 w 000095 h ppg3 - duty cycle register w 000096 h ppg3 - control status register low pcnl3 pcn3 r/w 000097 h ppg3 - control status register high pcnh3 r/w 000098 h ppg7-ppg4 - general control register 1 low gcn1l1 gcn11 r/w 000099 h ppg7-ppg4 - general control register 1 high gcn1h1 r/w 00009a h ppg7-ppg4 - general control register 2 low gcn2l1 gcn21 r/w 00009b h ppg7-ppg4 - general control register 2 high gcn2h1 r/w 00009c h ppg4 - timer register ptmr4 r 00009d h ppg4 - timer register r 00009e h ppg4 - period setting register pcsr4 w 00009f h ppg4 - period setting register w 0000a0 h ppg4 - duty cycle register pdut4 w i/o map mb96(f)35x (5 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 25 0000a1 h ppg4 - duty cycle register w 0000a2 h ppg4 - control status register low pcnl4 pcn4 r/w 0000a3 h ppg4 - control status register high pcnh4 r/w 0000a4 h ppg5 - timer register ptmr5 r 0000a5 h ppg5 - timer register r 0000a6 h ppg5 - period setting register pcsr5 w 0000a7 h ppg5 - period setting register w 0000a8 h ppg5 - duty cycle register pdut5 w 0000a9 h ppg5 - duty cycle register w 0000aa h ppg5 - control status register low pcnl5 pcn5 r/w 0000ab h ppg5 - control status register high pcnh5 r/w 0000ac h i2c0 - bus status register ibsr0 r 0000ad h i2c0 - bus control register ibcr0 r/w 0000ae h i2c0 - ten bit slave address register low itbal0 itba0 r/w 0000af h i2c0 - ten bit slave address register high itbah0 r/w 0000b0 h i2c0 - ten bit address mask register low itmkl0 itmk0 r/w 0000b1 h i2c0 - ten bit address mask register high itmkh0 r/w 0000b2 h i2c0 - seven bit slave address register isba0 r/w 0000b3 h i2c0 - seven bit address mask register ismk0 r/w 0000b4 h i2c0 - data register idar0 r/w 0000b5 h i2c0 - clock control register iccr0 r/w 0000b6 h - 0000d3 h reserved - 0000d4 h usart2 - serial mode register smr2 r/w 0000d5 h usart2 - serial control register scr2 r/w 0000d6 h usart2 - tx register tdr2 w 0000d6 h usart2 - rx register rdr2 r 0000d7 h usart2 - serial status ssr2 r/w 0000d8 h usart2 - control/com. register eccr2 r/w 0000d9 h usart2 - ext. status register escr2 r/w i/o map mb96(f)35x (6 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 26 fme-mb96350 rev 7 0000da h usart2 - baud rate generator register low bgrl2 bgr2 r/w 0000db h usart2 - baud rate generator register high bgrh2 r/w 0000dc h usart2 - extended serial interrupt register esir2 r/w 0000dd h reserved - 0000de h usart3 - serial mode register smr3 r/w 0000df h usart3 - serial control register scr3 r/w 0000e0 h usart3 - tx register tdr3 w 0000e0 h usart3 - rx register rdr3 r 0000e1 h usart3 - serial status ssr3 r/w 0000e2 h usart3 - control/com. register eccr3 r/w 0000e3 h usart3 - ext. status register escr3 r/w 0000e4 h usart3 - baud rate generator register low bgrl3 bgr3 r/w 0000e5 h usart3 - baud rate generator register high bgrh3 r/w 0000e6 h usart3 - extended serial interrupt register esir3 r/w 0000e7 h - 0000ef h reserved - 0000f0 h - 0000ff h external bus area extbus0 r/w 000100 h dma0 - buffer address pointer low byte bapl0 r/w 000101 h dma0 - buffer address pointer middle byte bapm0 r/w 000102 h dma0 - buffer address pointer high byte baph0 r/w 000103 h dma0 - dma control register dmacs0 r/w 000104 h dma0 - i/o register address pointer low byte ioal0 ioa0 r/w 000105 h dma0 - i/o register address pointer high byte ioah0 r/w 000106 h dma0 - data counter low byte dctl0 dct0 r/w 000107 h dma0 - data counter high byte dcth0 r/w 000108 h dma1 - buffer address pointer low byte bapl1 r/w 000109 h dma1 - buffer address pointer middle byte bapm1 r/w 00010a h dma1 - buffer address pointer high byte baph1 r/w 00010b h dma1 - dma control register dmacs1 r/w 00010c h dma1 - i/o register address pointer low byte ioal1 ioa1 r/w i/o map mb96(f)35x (7 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 27 00010d h dma1 - i/o register address pointer high byte ioah1 r/w 00010e h dma1 - data counter low byte dctl1 dct1 r/w 00010f h dma1 - data counter high byte dcth1 r/w 000110 h dma2 - buffer address pointer low byte bapl2 r/w 000111 h dma2 - buffer address pointer middle byte bapm2 r/w 000112 h dma2 - buffer address pointer high byte baph2 r/w 000113 h dma2 - dma control register dmacs2 r/w 000114 h dma2 - i/o register address pointer low byte ioal2 ioa2 r/w 000115 h dma2 - i/o register address pointer high byte ioah2 r/w 000116 h dma2 - data counter low byte dctl2 dct2 r/w 000117 h dma2 - data counter high byte dcth2 r/w 000118 h dma3 - buffer address pointer low byte bapl3 r/w 000119 h dma3 - buffer address pointer middle byte bapm3 r/w 00011a h dma3 - buffer address pointer high byte baph3 r/w 00011b h dma3 - dma control register dmacs3 r/w 00011c h dma3 - i/o register address pointer low byte ioal3 ioa3 r/w 00011d h dma3 - i/o register address pointer high byte ioah3 r/w 00011e h dma3 - data counter low byte dctl3 dct3 r/w 00011f h dma3 - data counter high byte dcth3 r/w 000120 h - 00017f h reserved - 000180 h - 00037f h cpu - general purpose registers (ram access) gpr_ram r/w 000380 h dma0 - interrupt select disel0 r/w 000381 h dma1 - interrupt select disel1 r/w 000382 h dma2 - interrupt select disel2 r/w 000383 h dma3 - interrupt select disel3 r/w 000384 h - 00038f h reserved - 000390 h dma - status register low byte dsrl dsr r/w 000391 h dma - status register high byte dsrh r/w i/o map mb96(f)35x (8 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 28 fme-mb96350 rev 7 000392 h dma - stop status register low byte dssrl dssr r/w 000393 h dma - stop status register high byte dssrh r/w 000394 h dma - enable register low byte derl der r/w 000395 h dma - enable register high byte derh r/w 000396 h - 00039f h reserved - 0003a0 h interrupt level register ilr icr r/w 0003a1 h interrupt index register idx r/w 0003a2 h interrupt vector table base register low tbrl tbr r/w 0003a3 h interrupt vector table base register high tbrh r/w 0003a4 h delayed interrupt register dirr r/w 0003a5 h non maskable interrupt register nmi r/w 0003a6 h - 0003ab h reserved - 0003ac h edsu communication interrupt selection low edsu2l edsu2 r/w 0003ad h edsu communication interrupt selection high edsu2h r/w 0003ae h rom mirror control register romm r/w 0003af h edsu con?uration register edsu r/w 0003b0 h memory patch control/status register ch 0/1 pfcs0 r/w 0003b1 h memory patch control/status register ch 0/1 r/w 0003b2 h memory patch control/status register ch 2/3 pfcs1 r/w 0003b3 h memory patch control/status register ch 2/3 r/w 0003b4 h memory patch control/status register ch 4/5 pfcs2 r/w 0003b5 h memory patch control/status register ch 4/5 r/w 0003b6 h memory patch control/status register ch 6/7 pfcs3 r/w 0003b7 h memory patch control/status register ch 6/7 r/w 0003b8 h memory patch function - patch address 0 low pfal0 r/w 0003b9 h memory patch function - patch address 0 middle pfam0 r/w 0003ba h memory patch function - patch address 0 high pfah0 r/w 0003bb h memory patch function - patch address 1 low pfal1 r/w 0003bc h memory patch function - patch address 1 middle pfam1 r/w i/o map mb96(f)35x (9 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 29 0003bd h memory patch function - patch address 1 high pfah1 r/w 0003be h memory patch function - patch address 2 low pfal2 r/w 0003bf h memory patch function - patch address 2 middle pfam2 r/w 0003c0 h memory patch function - patch address 2 high pfah2 r/w 0003c1 h memory patch function - patch address 3 low pfal3 r/w 0003c2 h memory patch function - patch address 3 middle pfam3 r/w 0003c3 h memory patch function - patch address 3 high pfah3 r/w 0003c4 h memory patch function - patch address 4 low pfal4 r/w 0003c5 h memory patch function - patch address 4 middle pfam4 r/w 0003c6 h memory patch function - patch address 4 high pfah4 r/w 0003c7 h memory patch function - patch address 5 low pfal5 r/w 0003c8 h memory patch function - patch address 5 middle pfam5 r/w 0003c9 h memory patch function - patch address 5 high pfah5 r/w 0003ca h memory patch function - patch address 6 low pfal6 r/w 0003cb h memory patch function - patch address 6 middle pfam6 r/w 0003cc h memory patch function - patch address 6 high pfah6 r/w 0003cd h memory patch function - patch address 7 low pfal7 r/w 0003ce h memory patch function - patch address 7 middle pfam7 r/w 0003cf h memory patch function - patch address 7 high pfah7 r/w 0003d0 h memory patch function - patch data 0 low pfdl0 pfd0 r/w 0003d1 h memory patch function - patch data 0 high pfdh0 r/w 0003d2 h memory patch function - patch data 1 low pfdl1 pfd1 r/w 0003d3 h memory patch function - patch data 1 high pfdh1 r/w 0003d4 h memory patch function - patch data 2 low pfdl2 pfd2 r/w 0003d5 h memory patch function - patch data 2 high pfdh2 r/w 0003d6 h memory patch function - patch data 3 low pfdl3 pfd3 r/w 0003d7 h memory patch function - patch data 3 high pfdh3 r/w 0003d8 h memory patch function - patch data 4 low pfdl4 pfd4 r/w 0003d9 h memory patch function - patch data 4 high pfdh4 r/w 0003da h memory patch function - patch data 5 low pfdl5 pfd5 r/w i/o map mb96(f)35x (10 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 30 fme-mb96350 rev 7 0003db h memory patch function - patch data 5 high pfdh5 r/w 0003dc h memory patch function - patch data 6 low pfdl6 pfd6 r/w 0003dd h memory patch function - patch data 6 high pfdh6 r/w 0003de h memory patch function - patch data 7 low pfdl7 pfd7 r/w 0003df h memory patch function - patch data 7 high pfdh7 r/w 0003e0 h - 0003f0 h reserved - 0003f1 h memory control status register a mcsra r/w 0003f2 h memory timing con?uration register a low mtcral mtcra r/w 0003f3 h memory timing con?uration register a high mtcrah r/w 0003f4 h - 0003f8 h reserved - 0003f9 h flash memory write control register 1 fmwc1 r/w 0003fa h flash memory write control register 2 fmwc2 r/w 0003fb h flash memory write control register 3 fmwc3 r/w 0003fc h flash memory write control register 4 fmwc4 r/w 0003fd h flash memory write control register 5 fmwc5 r/w 0003fe h - 0003ff h reserved - 000400 h standby mode control register smcr r/w 000401 h clock select register cksr r/w 000402 h clock stabilization select register ckssr r/w 000403 h clock monitor register ckmr r 000404 h clock frequency control register low ckfcrl ckfcr r/w 000405 h clock frequency control register high ckfcrh r/w 000406 h pll control register low pllcrl pllcr r/w 000407 h pll control register high pllcrh r/w 000408 h rc clock timer control register rctcr r/w 000409 h main clock timer control register mctcr r/w 00040a h sub clock timer control register sctcr r/w i/o map mb96(f)35x (11 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 31 00040b h reset cause and clock status register with clear function rccsrc r 00040c h reset con?uration register rcr r/w 00040d h reset cause and clock status register rccsr r 00040e h watch dog timer con?uration register wdtc r/w 00040f h watch dog timer clear pattern register wdtcp w 000410 h - 000414 h reserved - 000415 h clock output activation register coar r/w 000416 h clock output con?uration register 0 cocr0 r/w 000417 h clock output con?uration register 1 cocr1 r/w 000418 h clock modulator control register cmcr r/w 000419 h reserved - 00041a h clock modulator parameter register low cmprl cmpr r/w 00041b h clock modulator parameter register high cmprh r/w 00041c h - 00042b h reserved - 00042c h voltage regulator control register vrcr r/w 00042d h clock input and lvd control register cilcr r/w 00042e h - 00042f h reserved - 000430 h i/o port p00 - data direction register ddr00 r/w 000431 h i/o port p01 - data direction register ddr01 r/w 000432 h i/o port p02 - data direction register ddr02 r/w 000433 h i/o port p03 - data direction register ddr03 r/w 000434 h i/o port p04 - data direction register ddr04 r/w 000435 h i/o port p05 - data direction register ddr05 r/w 000436 h i/o port p06 - data direction register ddr06 r/w 000437 h - 000443 h reserved - 000444 h i/o port p00 - port input enable register pier00 r/w 000445 h i/o port p01 - port input enable register pier01 r/w i/o map mb96(f)35x (12 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 32 fme-mb96350 rev 7 000446 h i/o port p02 - port input enable register pier02 r/w 000447 h i/o port p03 - port input enable register pier03 r/w 000448 h i/o port p04 - port input enable register pier04 r/w 000449 h i/o port p05 - port input enable register pier05 r/w 00044a h i/o port p06 - port input enable register pier06 r/w 00044b h - 000457 h reserved - 000458 h i/o port p00 - port input level register pilr00 r/w 000459 h i/o port p01 - port input level register pilr01 r/w 00045a h i/o port p02 - port input level register pilr02 r/w 00045b h i/o port p03 - port input level register pilr03 r/w 00045c h i/o port p04 - port input level register pilr04 r/w 00045d h i/o port p05 - port input level register pilr05 r/w 00045e h i/o port p06 - port input level register pilr06 r/w 00045f h - 00046b h reserved - 00046c h i/o port p00 - extended port input level register epilr00 r/w 00046d h i/o port p01 - extended port input level register epilr01 r/w 00046e h i/o port p02 - extended port input level register epilr02 r/w 00046f h i/o port p03 - extended port input level register epilr03 r/w 000470 h i/o port p04 - extended port input level register epilr04 r/w 000471 h i/o port p05 - extended port input level register epilr05 r/w 000472 h i/o port p06 - extended port input level register epilr06 r/w 000473 h - 00047f h reserved - 000480 h i/o port p00 - port output drive register podr00 r/w 000481 h i/o port p01 - port output drive register podr01 r/w 000482 h i/o port p02 - port output drive register podr02 r/w 000483 h i/o port p03 - port output drive register podr03 r/w 000484 h i/o port p04 - port output drive register podr04 r/w 000485 h i/o port p05 - port output drive register podr05 r/w i/o map mb96(f)35x (13 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 33 000486 h i/o port p06 - port output drive register podr06 r/w 000487 h - 0004a7 h reserved - 0004a8 h i/o port p00 - pull-up resistor control register pucr00 r/w 0004a9 h i/o port p01 - pull-up resistor control register pucr01 r/w 0004aa h i/o port p02 - pull-up resistor control register pucr02 r/w 0004ab h i/o port p03 - pull-up resistor control register pucr03 r/w 0004ac h i/o port p04 - pull-up resistor control register pucr04 r/w 0004ad h i/o port p05 - pull-up resistor control register pucr05 r/w 0004ae h i/o port p06 - pull-up resistor control register pucr06 r/w 0004af h - 0004bb h reserved - 0004bc h i/o port p00 - external pin state register epsr00 r 0004bd h i/o port p01 - external pin state register epsr01 r 0004be h i/o port p02 - external pin state register epsr02 r 0004bf h i/o port p03 - external pin state register epsr03 r 0004c0 h i/o port p04 - external pin state register epsr04 r 0004c1 h i/o port p05 - external pin state register epsr05 r 0004c2 h i/o port p06 - external pin state register epsr06 r 0004c3 h - 0004cf h reserved - 0004d0 h adc analog input enable register 0 ader0 r/w 0004d1 h adc analog input enable register 1 ader1 r/w 0004d2 h adc analog input enable register 2 ader2 r/w 0004d3 h adc analog input enable register 3 ader3 r/w 0004d4 h adc analog input enable register 4 ader4 r/w 0004d5 h reserved - 0004d6 h peripheral resource relocation register 0 prrr0 r/w 0004d7 h peripheral resource relocation register 1 prrr1 r/w 0004d8 h peripheral resource relocation register 2 prrr2 r/w 0004d9 h peripheral resource relocation register 3 prrr3 r/w i/o map mb96(f)35x (14 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 34 fme-mb96350 rev 7 0004da h peripheral resource relocation register 4 prrr4 r/w 0004db h peripheral resource relocation register 5 prrr5 r/w 0004dc h peripheral resource relocation register 6 prrr6 r/w 0004dd h peripheral resource relocation register 7 prrr7 r/w 0004de h peripheral resource relocation register 8 prrr8 r/w 0004df h peripheral resource relocation register 9 prrr9 r/w 0004e0 h rtc - sub second register l wtbrl0 wtbr0 r/w 0004e1 h rtc - sub second register m wtbrh0 r/w 0004e2 h rtc - sub-second register h wtbr1 r/w 0004e3 h rtc - second register wtsr r/w 0004e4 h rtc - minutes wtmr r/w 0004e5 h rtc - hour wthr r/w 0004e6 h rtc - timer control extended register wtcer r/w 0004e7 h rtc - clock select register wtcksr r/w 0004e8 h rtc - timer control register low wtcrl wtcr r/w 0004e9 h rtc - timer control register high wtcrh r/w 0004ea h cal - calibration unit control register cucr r/w 0004eb h reserved - 0004ec h cal - duration timer data register low cutdl cutd r/w 0004ed h cal - duration timer data register high cutdh r/w 0004ee h cal - calibration timer register 2 low cutr2l cutr2 r 0004ef h cal - calibration timer register 2 high cutr2h r 0004f0 h cal - calibration timer register 1 low cutr1l cutr1 r 0004f1 h cal - calibration timer register 1 high cutr1h r 0004f2 h - 0004f9 h reserved - 0004fa h rlt - timer input select (for cascading) tmisr r/w 0004fb h - 0004ff h reserved - 000500 h frt2 - data register of free-running timer tcdt2 r/w 000501 h frt2 - data register of free-running timer r/w i/o map mb96(f)35x (15 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 35 000502 h frt2 - control status register of free-running timer low tccsl2 tccs2 r/w 000503 h frt2 - control status register of free-running timer high tccsh2 r/w 000504 h frt3 - data register of free-running timer tcdt3 r/w 000505 h frt3 - data register of free-running timer r/w 000506 h frt3 - control status register of free-running timer low tccsl3 tccs3 r/w 000507 h frt3 - control status register of free-running timer high tccsh3 r/w 000508 h - 000513 h reserved - 000514 h icu8/icu9 - control status register ics89 r/w 000515 h icu8/icu9 - edge register ice89 r/w 000516 h icu8 - capture register low ipcpl8 ipcp8 r 000517 h icu8 - capture register high ipcph8 r 000518 h icu9 - capture register low ipcpl9 ipcp9 r 000519 h icu9 - capture register high ipcph9 r 00051a h icu10/icu11 - control status register ics1011 r/w 00051b h icu10/icu11 - edge register ice1011 r/w 00051c h icu10 - capture register low ipcpl10 ipcp10 r 00051d h icu10 - capture register high ipcph10 r 00051e h icu11 - capture register low ipcpl11 ipcp11 r 00051f h icu11 - capture register high ipcph11 r 000520 h - 00053d h reserved - 00053e h usart7 - serial mode register smr7 r/w 00053f h usart7 - serial control register scr7 r/w 000540 h usart7 - serial tx register tdr7 w 000540 h usart7 - serial rx register rdr7 r 000541 h usart7 - serial status register ssr7 r/w 000542 h usart7 - ext. control/com. register eccr7 r/w i/o map mb96(f)35x (16 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 36 fme-mb96350 rev 7 000543 h usart7 - ext. status com. register escr7 r/w 000544 h usart7 - baud rate generator register low bgrl7 bgr7 r/w 000545 h usart7 - baud rate generator register high bgrh7 r/w 000546 h usart7 - extended serial interrupt register esir7 r/w 000547 h reserved - 000548 h usart8 - serial mode register smr8 r/w 000549 h usart8 - serial control register scr8 r/w 00054a h usart8 - serial tx register tdr8 w 00054a h usart8 - serial rx register rdr8 r 00054b h usart8 - serial status register ssr8 r/w 00054c h usart8 - ext. control/com. register eccr8 r/w 00054d h usart8 - ext. status com. register escr8 r/w 00054e h usart8 - baud rate generator register low bgrl8 bgr8 r/w 00054f h usart8 - baud rate generator register high bgrh8 r/w 000550 h usart8 - extended serial interrupt register esir8 r/w 000551 h - 000563 h reserved - 000564 h ppg6 - timer register ptmr6 r 000565 h ppg6 - timer register r 000566 h ppg6 - period setting register pcsr6 w 000567 h ppg6 - period setting register w 000568 h ppg6 - duty cycle register pdut6 w 000569 h ppg6 - duty cycle register w 00056a h ppg6 - control status register low pcnl6 pcn6 r/w 00056b h ppg6 - control status register high pcnh6 r/w 00056c h ppg7 - timer register ptmr7 r 00056d h ppg7 - timer register r 00056e h ppg7 - period setting register pcsr7 w 00056f h ppg7 - period setting register w 000570 h ppg7 - duty cycle register pdut7 w i/o map mb96(f)35x (17 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 37 000571 h ppg7 - duty cycle register w 000572 h ppg7 - control status register low pcnl7 pcn7 r/w 000573 h ppg7 - control status register high pcnh7 r/w 000574 h ppg11-ppg8 - general control register 1 low gcn1l2 gcn12 r/w 000575 h ppg11-ppg8 - general control register 1 high gcn1h2 r/w 000576 h ppg11-ppg8 - general control register 2 low gcn2l2 gcn22 r/w 000577 h ppg11-ppg8 - general control register 2 high gcn2h2 r/w 000578 h ppg8 - timer register ptmr8 r 000579 h ppg8 - timer register r 00057a h ppg8 - period setting register pcsr8 w 00057b h ppg8 - period setting register w 00057c h ppg8 - duty cycle register pdut8 w 00057d h ppg8 - duty cycle register w 00057e h ppg8 - control status register low pcnl8 pcn8 r/w 00057f h ppg8 - control status register high pcnh8 r/w 000580 h ppg9 - timer register ptmr9 r 000581 h ppg9 - timer register r 000582 h ppg9 - period setting register pcsr9 w 000583 h ppg9 - period setting register w 000584 h ppg9 - duty cycle register pdut9 w 000585 h ppg9 - duty cycle register w 000586 h ppg9 - control status register low pcnl9 pcn9 r/w 000587 h ppg9 - control status register high pcnh9 r/w 000588 h ppg10 - timer register ptmr10 r 000589 h ppg10 - timer register r 00058a h ppg10 - period setting register pcsr10 w 00058b h ppg10 - period setting register w 00058c h ppg10 - duty cycle register pdut10 w 00058d h ppg10 - duty cycle register w 00058e h ppg10 - control status register low pcnl10 pcn10 r/w i/o map mb96(f)35x (18 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 38 fme-mb96350 rev 7 00058f h ppg10 - control status register high pcnh10 r/w 000590 h ppg11 - timer register ptmr11 r 000591 h ppg11 - timer register r 000592 h ppg11 - period setting register pcsr11 w 000593 h ppg11 - period setting register w 000594 h ppg11 - duty cycle register pdut11 w 000595 h ppg11 - duty cycle register w 000596 h ppg11 - control status register low pcnl11 pcn11 r/w 000597 h ppg11 - control status register high pcnh11 r/w 000598 h ppg15-ppg12 - general control register 1 low gcn1l3 gcn13 r/w 000599 h ppg15-ppg12 - general control register 1 high gcn1h3 r/w 00059a h ppg15-ppg12 - general control register 2 low gcn2l3 gcn23 r/w 00059b h ppg15-ppg12 - general control register 2 high gcn2h3 r/w 00059c h ppg12 - timer register ptmr12 r 00059d h ppg12 - timer register r 00059e h ppg12 - period setting register pcsr12 w 00059f h ppg12 - period setting register w 0005a0 h ppg12 - duty cycle register pdut12 w 0005a1 h ppg12 - duty cycle register w 0005a2 h ppg12 - control status register low pcnl12 pcn12 r/w 0005a3 h ppg12 - control status register high pcnh12 r/w 0005a4 h ppg13 - timer register ptmr13 r 0005a5 h ppg13 - timer register r 0005a6 h ppg13 - period setting register pcsr13 w 0005a7 h ppg13 - period setting register w 0005a8 h ppg13 - duty cycle register pdut13 w 0005a9 h ppg13 - duty cycle register w 0005aa h ppg13 - control status register low pcnl13 pcn13 r/w 0005ab h ppg13 - control status register high pcnh13 r/w 0005ac h ppg14 - timer register ptmr14 r i/o map mb96(f)35x (19 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 39 0005ad h ppg14 - timer register r 0005ae h ppg14 - period setting register pcsr14 w 0005af h ppg14 - period setting register w 0005b0 h ppg14 - duty cycle register pdut14 w 0005b1 h ppg14 - duty cycle register w 0005b2 h ppg14 - control status register low pcnl14 pcn14 r/w 0005b3 h ppg14 - control status register high pcnh14 r/w 0005b4 h ppg15 - timer register ptmr15 r 0005b5 h ppg15 - timer register r 0005b6 h ppg15 - period setting register pcsr15 w 0005b7 h ppg15 - period setting register w 0005b8 h ppg15 - duty cycle register pdut15 w 0005b9 h ppg15 - duty cycle register w 0005ba h ppg15 - control status register low pcnl15 pcn15 r/w 0005bb h ppg15 - control status register high pcnh15 r/w 0005bc h ppg19-ppg16 - general control register 1 low gcn1l4 gcn14 r/w 0005bd h ppg19-ppg16 - general control register 1 high gcn1h4 r/w 0005be h ppg19-ppg16 - general control register 2 low gcn2l4 gcn24 r/w 0005bf h ppg19-ppg16 - general control register 2 high gcn2h4 r/w 0005c0 h ppg16 - timer register ptmr16 r 0005c1 h ppg16 - timer register r 0005c2 h ppg16 - period setting register pcsr16 w 0005c3 h ppg16 - period setting register w 0005c4 h ppg16 - duty cycle register pdut16 w 0005c5 h ppg16 - duty cycle register w 0005c6 h ppg16 - control status register low pcnl16 pcn16 r/w 0005c7 h ppg16 - control status register high pcnh16 r/w 0005c8 h ppg17 - timer register ptmr17 r 0005c9 h ppg17 - timer register r 0005ca h ppg17 - period setting register pcsr17 w i/o map mb96(f)35x (20 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 40 fme-mb96350 rev 7 0005cb h ppg17 - period setting register w 0005cc h ppg17 - duty cycle register pdut17 w 0005cd h ppg17 - duty cycle register w 0005ce h ppg17 - control status register low pcnl17 pcn17 r/w 0005cf h ppg17 - control status register high pcnh17 r/w 0005d0 h ppg18 - timer register ptmr18 r 0005d1 h ppg18 - timer register r 0005d2 h ppg18 - period setting register pcsr18 w 0005d3 h ppg18 - period setting register w 0005d4 h ppg18 - duty cycle register pdut18 w 0005d5 h ppg18 - duty cycle register w 0005d6 h ppg18 - control status register low pcnl18 pcn18 r/w 0005d7 h ppg18 - control status register high pcnh18 r/w 0005d8 h ppg19 - timer register ptmr19 r 0005d9 h ppg19 - timer register r 0005da h ppg19 - period setting register pcsr19 w 0005db h ppg19 - period setting register w 0005dc h ppg19 - duty cycle register pdut19 w 0005dd h ppg19 - duty cycle register w 0005de h ppg19 - control status register low pcnl19 pcn19 r/w 0005df h ppg19 - control status register high pcnh19 r/w 0005e0 h - 00065f h reserved - 000660 h peripheral resource relocation register 10 prrr10 r/w 000661 h peripheral resource relocation register 11 prrr11 r/w 000662 h peripheral resource relocation register 12 prrr12 r/w 000663 h peripheral resource relocation register 13 prrr13 w 000664 h - 0006df h reserved - 0006e0 h external bus - area con?uration register 0 low eacl0 eac0 r/w 0006e1 h external bus - area con?uration register 0 high each0 r/w i/o map mb96(f)35x (21 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 41 0006e2 h external bus - area con?uration register 1 low eacl1 eac1 r/w 0006e3 h external bus - area con?uration register 1 high each1 r/w 0006e4 h external bus - area con?uration register 2 low eacl2 eac2 r/w 0006e5 h external bus - area con?uration register 2 high each2 r/w 0006e6 h external bus - area con?uration register 3 low eacl3 eac3 r/w 0006e7 h external bus - area con?uration register 3 high each3 r/w 0006e8 h external bus - area con?uration register 4 low eacl4 eac4 r/w 0006e9 h external bus - area con?uration register 4 high each4 r/w 0006ea h external bus - area con?uration register 5 low eacl5 eac5 r/w 0006eb h external bus - area con?uration register 5 high each5 r/w 0006ec h external bus - area select register 2 eas2 r/w 0006ed h external bus - area select register 3 eas3 r/w 0006ee h external bus - area select register 4 eas4 r/w 0006ef h external bus - area select register 5 eas5 r/w 0006f0 h external bus - mode register ebm r/w 0006f1 h external bus - clock and function register ebcf r/w 0006f2 h external bus - address output enable register 0 ebae0 r/w 0006f3 h external bus - address output enable register 1 ebae1 r/w 0006f4 h external bus - address output enable register 2 ebae2 r/w 0006f5 h external bus - control signal register ebcs r/w 0006f6 h - 0007ff h reserved - 000800 h can1 - control register low ctrlrl1 ctrlr1 r/w 000801 h can1 - control register high (reserved) ctrlrh1 r 000802 h can1 - status register low statrl1 statr1 r/w 000803 h can1 - status register high (reserved) statrh1 r 000804 h can1 - error counter low (transmit) errcntl1 errcnt1 r 000805 h can1 - error counter high (receive) errcnth1 r 000806 h can1 - bit timing register low btrl1 btr1 r/w 000807 h can1 - bit timing register high btrh1 r/w i/o map mb96(f)35x (22 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 42 fme-mb96350 rev 7 000808 h can1 - interrupt register low intrl1 intr1 r 000809 h can1 - interrupt register high intrh1 r 00080a h can1 - test register low testrl1 testr1 r/w 00080b h can1 - test register high (reserved) testrh1 r 00080c h can1 - brp extension register low brperl1 brper1 r/w 00080d h can1 - brp extension register high (reserved) brperh1 r 00080e h - 00080f h reserved - 000810 h can1 - if1 command request register low if1creql1 if1creq1 r/w 000811 h can1 - if1 command request register high if1creqh1 r/w 000812 h can1 - if1 command mask register low if1cmskl1 if1cmsk1 r/w 000813 h can1 - if1 command mask register high (re- served) if1cmskh1 r 000814 h can1 - if1 mask 1 register low if1msk1l1 if1msk11 r/w 000815 h can1 - if1 mask 1 register high if1msk1h1 r/w 000816 h can1 - if1 mask 2 register low if1msk2l1 if1msk21 r/w 000817 h can1 - if1 mask 2 register high if1msk2h1 r/w 000818 h can1 - if1 arbitration 1 register low if1arb1l1 if1arb11 r/w 000819 h can1 - if1 arbitration 1 register high if1arb1h1 r/w 00081a h can1 - if1 arbitration 2 register low if1arb2l1 if1arb21 r/w 00081b h can1 - if1 arbitration 2 register high if1arb2h1 r/w 00081c h can1 - if1 message control register low if1mctrl1 if1mctr1 r/w 00081d h can1 - if1 message control register high if1mctrh1 r/w 00081e h can1 - if1 data a1 low if1dta1l1 if1dta11 r/w 00081f h can1 - if1 data a1 high if1dta1h1 r/w 000820 h can1 - if1 data a2 low if1dta2l1 if1dta21 r/w 000821 h can1 - if1 data a2 high if1dta2h1 r/w 000822 h can1 - if1 data b1 low if1dtb1l1 if1dtb11 r/w 000823 h can1 - if1 data b1 high if1dtb1h1 r/w 000824 h can1 - if1 data b2 low if1dtb2l1 if1dtb21 r/w 000825 h can1 - if1 data b2 high if1dtb2h1 r/w i/o map mb96(f)35x (23 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 43 000826 h - 00083f h reserved - 000840 h can1 - if2 command request register low if2creql1 if2creq1 r/w 000841 h can1 - if2 command request register high if2creqh1 r/w 000842 h can1 - if2 command mask register low if2cmskl1 if2cmsk1 r/w 000843 h can1 - if2 command mask register high (re- served) if2cmskh1 r 000844 h can1 - if2 mask 1 register low if2msk1l1 if2msk11 r/w 000845 h can1 - if2 mask 1 register high if2msk1h1 r/w 000846 h can1 - if2 mask 2 register low if2msk2l1 if2msk21 r/w 000847 h can1 - if2 mask 2 register high if2msk2h1 r/w 000848 h can1 - if2 arbitration 1 register low if2arb1l1 if2arb11 r/w 000849 h can1 - if2 arbitration 1 register high if2arb1h1 r/w 00084a h can1 - if2 arbitration 2 register low if2arb2l1 if2arb21 r/w 00084b h can1 - if2 arbitration 2 register high if2arb2h1 r/w 00084c h can1 - if2 message control register low if2mctrl1 if2mctr1 r/w 00084d h can1 - if2 message control register high if2mctrh1 r/w 00084e h can1 - if2 data a1 low if2dta1l1 if2dta11 r/w 00084f h can1 - if2 data a1 high if2dta1h1 r/w 000850 h can1 - if2 data a2 low if2dta2l1 if2dta21 r/w 000851 h can1 - if2 data a2 high if2dta2h1 r/w 000852 h can1 - if2 data b1 low if2dtb1l1 if2dtb11 r/w 000853 h can1 - if2 data b1 high if2dtb1h1 r/w 000854 h can1 - if2 data b2 low if2dtb2l1 if2dtb21 r/w 000855 h can1 - if2 data b2 high if2dtb2h1 r/w 000856 h - 00087f h reserved - 000880 h can1 - transmission request 1 register low treqr1l1 treqr11 r 000881 h can1 - transmission request 1 register high treqr1h1 r 000882 h can1 - transmission request 2 register low treqr2l1 treqr21 r 000883 h can1 - transmission request 2 register high treqr2h1 r i/o map mb96(f)35x (24 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 44 fme-mb96350 rev 7 000884 h - 00088f h reserved - 000890 h can1 - new data 1 register low newdt1l1 newdt11 r 000891 h can1 - new data 1 register high newdt1h1 r 000892 h can1 - new data 2 register low newdt2l1 newdt21 r 000893 h can1 - new data 2 register high newdt2h1 r 000894 h - 00089f h reserved - 0008a0 h can1 - interrupt pending 1 register low intpnd1l1 intpnd11 r 0008a1 h can1 - interrupt pending 1 register high intpnd1h1 r 0008a2 h can1 - interrupt pending 2 register low intpnd2l1 intpnd21 r 0008a3 h can1 - interrupt pending 2 register high intpnd2h1 r 0008a4 h - 0008af h reserved - 0008b0 h can1 - message valid 1 register low msgval1l1 msgval11 r 0008b1 h can1 - message valid 1 register high msgval1h1 r 0008b2 h can1 - message valid 2 register low msgval2l1 msgval21 r 0008b3 h can1 - message valid 2 register high msgval2h1 r 0008b4 h - 0008cd h reserved - 0008ce h can1 - output enable register coer1 r/w 0008cf h - 0008ff h reserved - 000900 h can2 - control register low ctrlrl2 ctrlr2 r/w 000901 h can2 - control register high (reserved) ctrlrh2 r 000902 h can2 - status register low statrl2 statr2 r/w 000903 h can2 - status register high (reserved) statrh2 r 000904 h can2 - error counter low (transmit) errcntl2 errcnt2 r 000905 h can2 - error counter high (receive) errcnth2 r 000906 h can2 - bit timing register low btrl2 btr2 r/w 000907 h can2 - bit timing register high btrh2 r/w 000908 h can2 - interrupt register low intrl2 intr2 r i/o map mb96(f)35x (25 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 45 000909 h can2 - interrupt register high intrh2 r 00090a h can2 - test register low testrl2 testr2 r/w 00090b h can2 - test register high (reserved) testrh2 r 00090c h can2 - brp extension register low brperl2 brper2 r/w 00090d h can2 - brp extension register high (reserved) brperh2 r 00090e h - 00090f h reserved - 000910 h can2 - if1 command request register low if1creql2 if1creq2 r/w 000911 h can2 - if1 command request register high if1creqh2 r/w 000912 h can2 - if1 command mask register low if1cmskl2 if1cmsk2 r/w 000913 h can2 - if1 command mask register high (re- served) if1cmskh2 r 000914 h can2 - if1 mask 1 register low if1msk1l2 if1msk12 r/w 000915 h can2 - if1 mask 1 register high if1msk1h2 r/w 000916 h can2 - if1 mask 2 register low if1msk2l2 if1msk22 r/w 000917 h can2 - if1 mask 2 register high if1msk2h2 r/w 000918 h can2 - if1 arbitration 1 register low if1arb1l2 if1arb12 r/w 000919 h can2 - if1 arbitration 1 register high if1arb1h2 r/w 00091a h can2 - if1 arbitration 2 register low if1arb2l2 if1arb22 r/w 00091b h can2 - if1 arbitration 2 register high if1arb2h2 r/w 00091c h can2 - if1 message control register low if1mctrl2 if1mctr2 r/w 00091d h can2 - if1 message control register high if1mctrh2 r/w 00091e h can2 - if1 data a1 low if1dta1l2 if1dta12 r/w 00091f h can2 - if1 data a1 high if1dta1h2 r/w 000920 h can2 - if1 data a2 low if1dta2l2 if1dta22 r/w 000921 h can2 - if1 data a2 high if1dta2h2 r/w 000922 h can2 - if1 data b1 low if1dtb1l2 if1dtb12 r/w 000923 h can2 - if1 data b1 high if1dtb1h2 r/w 000924 h can2 - if1 data b2 low if1dtb2l2 if1dtb22 r/w 000925 h can2 - if1 data b2 high if1dtb2h2 r/w i/o map mb96(f)35x (26 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 46 fme-mb96350 rev 7 000926 h - 00093f h reserved - 000940 h can2 - if2 command request register low if2creql2 if2creq2 r/w 000941 h can2 - if2 command request register high if2creqh2 r/w 000942 h can2 - if2 command mask register low if2cmskl2 if2cmsk2 r/w 000943 h can2 - if2 command mask register high (re- served) if2cmskh2 r 000944 h can2 - if2 mask 1 register low if2msk1l2 if2msk12 r/w 000945 h can2 - if2 mask 1 register high if2msk1h2 r/w 000946 h can2 - if2 mask 2 register low if2msk2l2 if2msk22 r/w 000947 h can2 - if2 mask 2 register high if2msk2h2 r/w 000948 h can2 - if2 arbitration 1 register low if2arb1l2 if2arb12 r/w 000949 h can2 - if2 arbitration 1 register high if2arb1h2 r/w 00094a h can2 - if2 arbitration 2 register low if2arb2l2 if2arb22 r/w 00094b h can2 - if2 arbitration 2 register high if2arb2h2 r/w 00094c h can2 - if2 message control register low if2mctrl2 if2mctr2 r/w 00094d h can2 - if2 message control register high if2mctrh2 r/w 00094e h can2 - if2 data a1 low if2dta1l2 if2dta12 r/w 00094f h can2 - if2 data a1 high if2dta1h2 r/w 000950 h can2 - if2 data a2 low if2dta2l2 if2dta22 r/w 000951 h can2 - if2 data a2 high if2dta2h2 r/w 000952 h can2 - if2 data b1 low if2dtb1l2 if2dtb12 r/w 000953 h can2 - if2 data b1 high if2dtb1h2 r/w 000954 h can2 - if2 data b2 low if2dtb2l2 if2dtb22 r/w 000955 h can2 - if2 data b2 high if2dtb2h2 r/w 000956 h - 00097f h reserved - 000980 h can2 - transmission request 1 register low treqr1l2 treqr12 r 000981 h can2 - transmission request 1 register high treqr1h2 r 000982 h can2 - transmission request 2 register low treqr2l2 treqr22 r 000983 h can2 - transmission request 2 register high treqr2h2 r i/o map mb96(f)35x (27 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series fme-mb96350 rev 7 47 note: any write access to reserved addresses in the i/o map should not be performed. a read access to a reserved address results in reading ?? registers of resources which are described in this table, but which are not supported by the device, should also be handled as ?eserved? 000984 h - 00098f h reserved - 000990 h can2 - new data 1 register low newdt1l2 newdt12 r 000991 h can2 - new data 1 register high newdt1h2 r 000992 h can2 - new data 2 register low newdt2l2 newdt22 r 000993 h can2 - new data 2 register high newdt2h2 r 000994 h - 00099f h reserved - 0009a0 h can2 - interrupt pending 1 register low intpnd1l2 intpnd12 r 0009a1 h can2 - interrupt pending 1 register high intpnd1h2 r 0009a2 h can2 - interrupt pending 2 register low intpnd2l2 intpnd22 r 0009a3 h can2 - interrupt pending 2 register high intpnd2h2 r 0009a4 h - 0009af h reserved - 0009b0 h can2 - message valid 1 register low msgval1l2 msgval12 r 0009b1 h can2 - message valid 1 register high msgval1h2 r 0009b2 h can2 - message valid 2 register low msgval2l2 msgval22 r 0009b3 h can2 - message valid 2 register high msgval2h2 r 0009b4 h - 0009cd h reserved - 0009ce h can2 - output enable register coer2 r/w 0009cf h - 000bff h reserved - i/o map mb96(f)35x (28 of 28) address register abbreviation 8-bit access abbreviation 16-bit access access www.datasheet.in mb96350 series 48 fme-mb96350 rev 7 interrupt vector table interrupt vector table mb96(f)35x (1 of 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description 0 3fc h callv0 no - 1 3f8 h callv1 no - 2 3f4 h callv2 no - 3 3f0 h callv3 no - 4 3ec h callv4 no - 5 3e8 h callv5 no - 6 3e4 h callv6 no - 7 3e0 h callv7 no - 8 3dc h reset no - 9 3d8 h int9 no - 10 3d4 h exception no - 11 3d0 h nmi no - non-maskable interrupt 12 3cc h dly no 12 delayed interrupt 13 3c8 h rc_timer no 13 rc timer 14 3c4 h mc_timer no 14 main clock timer 15 3c0 h sc_timer no 15 sub clock timer 16 3bc h pll_unlock no 16 reserved 17 3b8 h extint0 yes 17 external interrupt 0 18 3b4 h reserved 19 3b0 h extint2 yes 19 external interrupt 2 20 3ac h extint3 yes 20 external interrupt 3 21 3a8 h extint4 yes 21 external interrupt 4 22 3a4 h reserved 23 3a0 h extint7 yes 23 external interrupt 7 24 39c h extint8 yes 24 external interrupt 8 25 398 h extint9 yes 25 external interrupt 9 26 394 h extint10 yes 26 external interrupt 10 27 390 h extint11 yes 27 external interrupt 11 28 38c h extint12 yes 28 external interrupt 12 29 388 h extint13 yes 29 external interrupt 13 30 384 h extint14 yes 30 external interrupt 14 31 380 h extint15 yes 31 external interrupt 15 32 37c h can1 no 32 can controller 1 (only mb96f356y/r) www.datasheet.in mb96350 series fme-mb96350 rev 7 49 33 378 h can2 no 33 can controller 2 (only mb96f356y/r and MB96F353r/f355r) 34 374 h ppg0 yes 34 programmable pulse generator 0 35 370 h ppg1 yes 35 programmable pulse generator 1 36 36c h ppg2 yes 36 programmable pulse generator 2 37 368 h ppg3 yes 37 programmable pulse generator 3 38 364 h ppg4 yes 38 programmable pulse generator 4 39 360 ppg5 yes 39 programmable pulse generator 5 40 35c h ppg6 yes 40 programmable pulse generator 6 41 358 h ppg7 yes 41 programmable pulse generator 7 42 354 h ppg8 yes 42 programmable pulse generator 8 43 350 h ppg9 yes 43 programmable pulse generator 9 44 34c h ppg10 yes 44 programmable pulse generator 10 45 348 h ppg11 yes 45 programmable pulse generator 11 46 344 h ppg12 yes 46 programmable pulse generator 12 47 340 h ppg13 yes 47 programmable pulse generator 13 48 33c h ppg14 yes 48 programmable pulse generator 14 49 338 h ppg15 yes 49 programmable pulse generator 15 50 334 h ppg16 yes 50 programmable pulse generator 16 51 330 h ppg17 yes 51 programmable pulse generator 17 52 32c h ppg18 yes 52 programmable pulse generator 18 53 328 h ppg19 yes 53 programmable pulse generator 19 54 324 h rlt0 yes 54 reload timer 0 55 320 h rlt1 yes 55 reload timer 1 56 31c h rlt2 yes 56 reload timer 2 57 318 h rlt3 yes 57 reload timer 3 58 314 h ppgrlt yes 58 reload timer 6 - dedicated for ppg 59 310 h icu0 yes 59 input capture unit 0 60 30c h icu1 yes 60 input capture unit 1 61 308 h reserved 62 304 h reserved 63 300 h icu4 yes 63 input capture unit 4 64 2fc h icu5 yes 64 input capture unit 5 65 2f8 h icu6 yes 65 input capture unit 6 66 2f4 h icu7 yes 66 input capture unit 7 interrupt vector table mb96(f)35x (2 of 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description www.datasheet.in mb96350 series 50 fme-mb96350 rev 7 67 2f0 h reserved 68 2ec h icu9 yes 68 input capture unit 9 69 2e8 h icu10 yes 69 input capture unit 10 70 2e4 h reserved 71 2e0 h ocu4 yes 71 output compare unit 4 72 2dc h ocu5 yes 72 output compare unit 5 73 2d8 h ocu6 yes 73 output compare unit 6 74 2d4 h ocu7 yes 74 output compare unit 7 75 2d0 h reserved 76 2cc h reserved 77 2c8 h frt0 yes 77 free running timer 0 78 2c4 h frt1 yes 78 free running timer 1 79 2c0 h frt2 yes 79 free running timer 2 80 2bc h frt3 yes 80 free running timer 3 81 2b8 h rtc0 no 81 real timer clock 82 2b4 h cal0 no 82 clock calibration unit 83 2b0 h iic0 yes 83 i2c interface 84 2ac h adc0 yes 84 a/d converter 85 2a8 h linr2 yes 85 lin usart 2 rx 86 2a4 h lint2 yes 86 lin usart 2 tx 87 2a0 h linr3 yes 87 lin usart 3 rx 88 29c h lint3 yes 88 lin usart 3 tx 89 298 h linr7 yes 89 lin usart 7 rx 90 294 h lint7 yes 90 lin usart 7 tx 91 290 h linr8 yes 91 lin usart 8 rx 92 28c h lint8 yes 92 lin usart 8 tx 93 288 h flash_a no 93 flash memory a (only flash devices) interrupt vector table mb96(f)35x (3 of 3) vector number offset in vector ta- ble vector name cleared by dma index in icr to pro- gram description www.datasheet.in mb96350 series fme-mb96350 rev 7 51 handling devices special care is required for the following when handling the device: latch-up prevention unused pins handling external clock usage unused sub clock signal notes on pll clock mode operation power supply pins (v cc /v ss ) crystal oscillator circuit turn on sequence of power supply to a/d converter and analog inputs pin handling when not using the a/d converter notes on energization stabilization of power supply voltage serial communication 1. latch-up prevention cmos ic chips may suffer latch-up under the following conditions: a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc pins and v ss pins. latch-up may increase the power supply current dramatically, causing thermal damages to the device. 2. unused pins handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the device. they must therefore be pulled up or pulled down through resistors. to prevent latch-up, those resistors should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull-up/pull-down resistor as described above. 3. external clock usage the permitted frequency range of an external clock depends on the oscillator type and con?uration. see ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 1. single phase external clock when using a single phase external clock, x0 (x0a) pin must be driven and x1 (x1a) pin left open. x0 x1 www.datasheet.in mb96350 series 52 fme-mb96350 rev 7 2. opposite phase external clock when using an opposite phase external clock, x1 (x1a) must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. 4. unused sub clock signal if the pins x0a and x1a are not connected to an oscillator, a pull-down resistor must be connected on the x0a pin and the x1a pin must be left open. 5. notes on pll clock mode operation if the pll clock mode is selected and no external oscillator is operating or no external clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 6. power supply pins (v cc / v ss ) it is required that all v cc -level as well as all v ss -level power supply pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. v cc and v ss must be connected to the device from the power supply with lowest possible impedance. as a measure against power supply noise, it is required to connect a bypass capacitor of about 0.1 f between v cc and v ss as close as possible to v cc and v ss pins. 7. crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surrounding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu or resonator/mcu system at the quartz or resonator manufacturer, especially when using low-q resonators at higher frequencies. 8. turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh, avrl) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the digital power off after turning the a/d converter supply and analog inputs off. in this case, the voltage must not exceed avrh or av cc (turning the analog and digital power supplies simultaneously on or off is acceptable). 9. pin handling when not using the a/d converter it is required to connect the unused pins of the a/d converter as av cc = v cc , av ss = avrh = avrl = v ss . 10. notes on power-on to prevent malfunction of the internal voltage regulator, supply voltage pro?e while turning the power supply on should be slower than 50 s from 0.2 v to 2.7 v. x0 x1 www.datasheet.in mb96350 series fme-mb96350 rev 7 53 11. stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety range of the vcc power supply voltage, a malfunction may occur. the vcc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that vcc ripple ?ctuations (peak to peak value) in the commercial frequencies (50 to 60 hz) fall within 10% of the standard vcc power supply voltage and the transient ?ctuation rate becomes 0.1v/ s or less in instantaneous ?ctuation for power supply switching. 12. serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs. www.datasheet.in mb96350 series 54 fme-mb96350 rev 7 electrical characteristics 1. absolute maximum ratings *1: av cc and v cc must be set to the same voltage. it is required that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc neither when the power is switched on. parameter symbol rating unit remarks min max power supply voltage v cc v ss - 0.3 v ss + 6.0 v av cc v ss - 0.3 v ss + 6.0 v v cc = av cc *1 ad converter voltage references avrh, avrl v ss - 0.3 v ss + 6.0 v av cc avrh, av cc avrl, avrh > avrl, avrl av ss input voltage v i v ss - 0.3 v ss + 6.0 v v i v cc + 0.3v *2 output voltage v o v ss - 0.3 v ss + 6.0 v v o v cc + 0.3v *2 maximum clamp current i clamp -4.0 +4.0 ma applicable to general purpose i/o pins *3 total maximum clamp current |i clamp | - 40 ma applicable to general purpose i/o pins *3 ??level maximum output current i ol1 - 15 ma normal outputs with driving strength set to 5ma ??level average output current i olav1 - 5 ma normal outputs with driving strength set to 5ma ??level maximum overall output current i ol1 - 100 ma normal outputs ??level average overall output current i olav1 - 50 ma normal outputs ??level maximum output current i oh1 - -15 ma normal outputs with driving strength set to 5ma ??level average output current i ohav1 - -5 ma normal outputs with driving strength set to 5ma ? level maximum overall output current i oh1 - -100 ma normal outputs ??level average overall output current i ohav1 - -50 ma normal outputs permitted power dissipation (flash de- vices) *4 p d - 320 *5 mw t a =105 o c - 640 *5 mw t a =85 o c - 800 *5 mw t a =75 o c - 400 *5 mw t a =125 o c, no flash program/ erase *6 - 560 *5 mw t a =115 o c, no flash program/ erase *6 operating ambient temperature t a 0 +70 o c mb96v300b -40 +105 -40 +125 *6 storage temperature t stg -55 +150 o c www.datasheet.in mb96350 series fme-mb96350 rev 7 55 *2: v i and v o should not exceed v cc + 0.3 v. v i should also not exceed the speci?d ratings. however if the maximum current to/from a input is limited by some means with external components, the i clamp rating super- sedes the v i rating. input/output voltages of standard ports depend on v cc. *3: ? applicable to all general purpose i/o pins (pnn_m) ? use within recommended operating conditions. ? use at dc voltage (current) ? the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not ?ed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suf?ient to operate the power reset (except devices with persistent low voltage reset in internal vector mode). ? sample recommended circuits: *4: the maximum permitted power dissipation depends on the ambient temperature, the air ?w velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: p d = p io + p int p io = (v ol * i ol + v oh * i oh ) (io load power dissipation, sum is performed on all io ports) p int = v cc * (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the ?c characteristics and depends on the selected operation mode and clock frequency and the usage of functions like flash programming or the clock modulator. i a is the analog current consumption into av cc . *5: worst case value for a package mounted on single layer pcb at speci?d t a without air ?w. *6: please contact fujitsu for reliability limitations when using under these conditions. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r protective diode limiting resistance +b input (0v to 16v) www.datasheet.in mb96350 series 56 fme-mb96350 rev 7 2. recommended operating conditions warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device s electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc 3.0 - 5.5 v smoothing capacitor at c pin c s 3.5 4.7 15 f use a x7r ceramic capacitor or a capacitor that has similar fre- quency characteristics www.datasheet.in mb96350 series fme-mb96350 rev 7 57 3. dc characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit remarks min typ max input h voltage v ih port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected 0.8 v cc - v cc + 0.3 v cmos hysteresis 0.7/0.3 input se- lected 0.7 v cc - v cc + 0.3 vv cc 4.5v 0.74 v cc - v cc + 0.3 vv cc < 4.5v automotive hysteresis input selected 0.8 v cc - v cc + 0.3 v ttl input select- ed 2.0 - v cc + 0.3 v v ihx0f x0 external clock in ?ast clock input mode 0.8 v cc - v cc + 0.3 v v ihx0s x0,x1, x0a,x1a external clock in ?scillation mode 2.5 - v cc + 0.3 v v ihr rstx - 0.8 v cc - v cc + 0.3 v cmos hysteresis in- put v ihm md2-md0 - v cc - 0.3 - v cc + 0.3 v input l voltage v il port inputs pnn_m cmos hysteresis 0.8/0.2 input se- lected v ss - 0.3 - 0.2 v cc v cmos hysteresis 0.7/0.3 input se- lected v ss - 0.3 - 0.3 v cc v automotive hysteresis input selected v ss - 0.3 - 0.5 v cc vv cc 4.5v v ss - 0.3 - 0.46 v cc v cc < 4.5v ttl input select- ed v ss - 0.3 - 0.8 v v ilx0f x0 external clock in ?ast clock input mode v ss - 0.3 - 0.2 v cc v v ilx0s x0,x1, x0a,x1a external clock in ?scillation mode v ss - 0.3 - 0.4 v v ilr rstx - v ss - 0.3 - 0.2 v cc v cmos hysteresis in- put v ilm md2-md0 - v ss - 0.3 - v ss + 0.3 v www.datasheet.in mb96350 series 58 fme-mb96350 rev 7 output h voltage v oh2 normal outputs 4.5v v cc 5.5v i oh = -2ma v cc - 0.5 -- v driving strength set to 2ma (podr:od=1) 3.0v v cc < 4.5v i oh = -1.6ma v oh5 normal outputs 4.5v v cc 5.5v i oh = -5ma v cc - 0.5 -- v driving strength set to 5ma (podr:od=0) 3.0v v cc < 4.5v i oh = -3ma v oh3 3ma out- puts 4.5v v cc 5.5v i oh = -3ma v cc - 0.5 -- v i/o circuit type ? 3.0v v cc < 4.5v i oh = -2ma output l voltage v ol2 normal outputs 4.5v v cc 5.5v i ol = +2ma - - 0.4 v driving strength set to 2ma (podr:od=1) 3.0v v cc < 4.5v i ol = +1.6ma v ol5 normal outputs 4.5v v cc 5.5v i ol = +5ma - - 0.4 v driving strength set to 5ma (podr:od=0) 3.0v v cc < 4.5v i ol = +3ma v ol3 3ma out- puts 3.0v v cc 5.5v i ol = +3ma - - 0.4 v i/o circuit type ? input leak current i il pnn_m v ss < v i < v cc av ss ,avrl mb96350 series 60 fme-mb96350 rev 7 power supply cur- rent in run modes* i ccmain main run mode with clks1/2 = clkb = clkp1/2 = 4mhz 1 flash/rom wait state (clkpll, clksc and clkrc stopped) +25?c 4 5 ma MB96F353/f355 +125?c 4.7 8 +25?c 4.2 5.2 ma mb96f356 +125?c 4.9 8.2 i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = 2mhz 1 flash/rom wait state (clkmc, clkpll and clksc stopped) +25?c 2.5 3.5 ma MB96F353/f355 +125?c 3.2 6.5 +25?c 2.7 3.7 ma mb96f356 +125?c 3.4 6.7 i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 0 1 flash/rom wait state (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.18 0.3 ma MB96F353/f355 +125?c 0.73 3.1 +25?c 0.4 0.6 ma mb96f356 +125?c 0.95 3.4 rc run mode with clks1/2 = clkb = clkp1/2 = 100khz, smcr:lpms = 1 1 flash/rom wait state (clkmc, clkpll and clksc stopped. voltage regulator in low power mode, no flash program- ming/erasing allowed) +25?c 0.15 0.25 ma MB96F353/f355/ f356 +125?c 0.7 3.05 i ccsub sub run mode with clks1/2 = clkb = clkp1/2 = 32khz 1 flash/rom wait state (clkmc, clkpll and clkrc stopped, no flash programming/erasing al- lowed) +25?c 0.1 0.2 ma MB96F353/f355/ f356 +125?c 0.65 3 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit www.datasheet.in mb96350 series fme-mb96350 rev 7 61 power supply cur- rent in sleep modes* i ccspll pll sleep mode with clks1/2 = clkp1 = 16mhz, clkp2 = 8mhz (clkrc and clksc stopped) +25?c 4 6 ma MB96F353/f355/ f356 +125?c 4.7 9 pll sleep mode with clks1/2 = clkp1 = 32mhz, clkp2 = 16mhz (clkrc and clksc stopped) +25?c 7 9.5 ma MB96F353/f355/ f356 +125?c 8 12.5 pll sleep mode with clks1/2 = 48mhz, clkp1/2 = 24mhz (clkrc and clksc stopped) +25?c 7 9 ma MB96F353/f355/ f356 +125?c 8 12 pll sleep mode with clks1/2 = clkp1= 56mhz, clkp2 = 28mhz (clkrc and clksc stopped. core voltage at 1.9v) +25?c 11 14.5 ma MB96F353/f355/ f356 +125?c 12 17.5 pll sleep mode with clks1/2 = 96mhz, clkp1= 48mhz, clkp2 = 24mhz (clkrc and clksc stopped. core voltage at 1.9v) +25?c 12 15 ma MB96F353/f355/ f356 +125?c 13 18 i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz (clkpll, clksc and clkrc stopped) +25?c 1 1.3 ma MB96F353/f355 +125?c 1.6 4.1 +25?c 1.3 1.8 ma mb96f356 +125?c 1.9 4.6 i ccsrch rc sleep mode with clks1/2 = clkp1/2 = 2mhz (clkmc, clkpll and clksc stopped) +25?c 0.55 1.1 ma MB96F353/f355 +125?c 1.15 3.9 +25?c 0.8 1.4 ma mb96f356 +125?c 1.4 4.2 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit www.datasheet.in mb96350 series 62 fme-mb96350 rev 7 power supply cur- rent in sleep modes* i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.08 0.2 ma MB96F353/f355 +125?c 0.59 2.95 +25?c 0.3 0.5 ma mb96f356 +125?c 0.8 3.3 rc sleep mode with clks1/2 = clkp1/2 = 100khz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.05 0.15 ma MB96F353/f355/ f356 +125?c 0.56 2.9 i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz (clkmc, clkpll and clkrc stopped) +25?c 0.04 0.12 ma MB96F353/f355/ f356 +125?c 0.54 2.9 power supply cur- rent in timer modes* i cctpll pll timer mode with clkmc = 4mhz, clkpll = 48mhz (clkrc and clksc stopped) +25?c 1.3 1.8 ma MB96F353/f355 +125?c 1.9 4.8 +25?c 1.5 2 ma mb96f356 +125?c 2.1 5 i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped. voltage regulator in high power mode) +25?c 0.11 0.2 ma MB96F353/f355 +125?c 0.63 3 +25?c 0.35 0.5 ma mb96f356 +125?c 0.85 3.3 main timer mode with clkmc = 4mhz, smcr:lpmss = 1 (clkpll, clkrc and clksc stopped. voltage regulator in low power mode) +25?c 0.08 0.15 ma MB96F353/f355/ f356 +125?c 0.6 2.9 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit www.datasheet.in mb96350 series fme-mb96350 rev 7 63 power supply cur- rent in timer modes* i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.1 0.2 ma MB96F353/f355 +125?c 0.63 3 +25?c 0.35 0.5 ma mb96f356 +125?c 0.85 3.3 rc timer mode with clkrc = 2mhz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.07 0.15 ma MB96F353/f355/ f356 +125?c 0.6 2.9 i cctrcl rc timer mode with clkrc = 100khz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped. voltage regulator in high power mode) +25?c 0.06 0.15 ma MB96F353/f355 +125?c 0.56 2.95 +25?c 0.3 0.45 ma mb96f356 +125?c 0.8 3.2 rc timer mode with clkrc = 100khz, smcr:lpmss = 1 (clkmc, clkpll and clksc stopped. voltage regulator in low power mode) +25?c 0.03 0.1 ma MB96F353/f355/ f356 +125?c 0.53 2.85 i cctsub sub timer mode with clksc = 32khz (clkmc, clkpll and clkrc stopped) +25?c 0.035 0.1 ma MB96F353/f355/ f356 +125?c 0.53 2.85 power supply cur- rent in stop mode i cch vrcr:lpmb[2:0] = 110 b (core voltage at 1.8v) +25?c 0.02 0.08 ma MB96F353/f355/ f356 +125?c 0.52 2.8 vrcr:lpmb[2:0] = 000 b (core voltage at 1.2v) +25?c 0.015 0.06 ma MB96F353/f355/ f356 +125?c 0.4 2.3 power supply cur- rent for active low voltage detector i cclvd low voltage detector en- abled (rcr:lvde = 1) +25?c 5 10 a MB96F353/f355 must be added to all current above +125?c 7 20 a +25?c 90 140 a mb96f356 must be added to all current above +125?c 100 150 (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit www.datasheet.in mb96350 series 64 fme-mb96350 rev 7 power supply cur- rent for active clock modulator i ccclomo clock modulator enabled (cmcr:pdx = 1) - 3 4.5 ma must be added to all current above flash write/erase current i ccflash current for one flash module -1540ma must be added to all current above input capacitance c in --515pf other than c, av cc , av ss , avrh, avrl, v cc , v ss * the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter ?tandby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol condition (at t a ) value remarks typ max unit www.datasheet.in mb96350 series fme-mb96350 rev 7 65 4. ac characteristics source clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3 - 16 mhz when using a crystal oscillator, pll off 0 - 16 mhz when using an opposite phase external clock, pll off 3.5 - 16 mhz when using a crystal oscillator or oppo- site phase external clock, pll on clock frequency f fci x0 0 - 56 mhz when using a single phase external clock in fast clock input mode , pll off 3.5 - 56 mhz when using a single phase external clock in fast clock input mode , pll on clock frequency f cl x0a, x1a 32 32.768 100 khz when using an oscillation circuit 0 - 100 khz when using an opposite phase external clock x0a 0 - 50 khz when using a single phase external clock clock frequency f cr - 50 100 200 khz when using slow frequency of rc oscil- lator 1 2 4 mhz when using fast frequency of rc oscil- lator rc clock stabili- zation time t rcstab - 64 or 256 rc clock cycles applied after any reset and when acti- vating the rc oscillator. mb96f356: 64 cycles others: 256 cycles pll clock fre- quency f clkvco - 64 - 200 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew --- 5ns for clkmc (pll input clock) 4 mhz, jitter coming from external oscillator, crystal or resonator is not covered input clock pulse width p wh , p wl x0,x1 8 - - ns duty ratio is about 30% to 70% input clock pulse width p whl , p wll x0a,x1a 5 - - s www.datasheet.in mb96350 series 66 fme-mb96350 rev 7 x0 t cyl p wh p wl v il v ih x0a t cyll p whl p wll v il v ih www.datasheet.in mb96350 series fme-mb96350 rev 7 67 internal clock timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol core voltage settings unit remarks 1.8v 1.9v min max min max internal system clock fre- quency (clks1 and clks2) f clks1 , f clks2 0 92 0 96 mhz others than below 0 88 0 96 mhz mb96f356 internal cpu clock fre- quency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 052056mhz internal peripheral clock frequency (clkp2) f clkp2 028032mhz www.datasheet.in mb96350 series 68 fme-mb96350 rev 7 external reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max reset input time t rstl rstx 500 - - ns 0.2 v cc rstx t rstl 0.2 v cc www.datasheet.in mb96350 series fme-mb96350 rev 7 69 power on reset timing (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max power on rise time t r vcc 0.05 - 30 ms power off time t off vcc 1 - - ms 0.2 v t r 2.7v t off 0.2 v 0.2 v if the power supply is changed too rapidly, a power-on reset may occur. we recommend a smooth startup by restraining voltages when changing the power supply voltage during operation, as shown in the ?ure below. 3 v v cc v cc rising edge of 50 mv/ms maximum is allowed www.datasheet.in mb96350 series 70 fme-mb96350 rev 7 external input timing note : relocated resource inputs have same characteristics (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin condition value unit used pin input func- tion min max input pulse width t inh t inl intn(_r) ? 200 ? ns external interrupt nmi(_r) nmi pnn_m 2*t clkp1 + 200 (t clkp1 =1/ f clkp1 ) ? ns general purpose io tinn(_r) reload timer ttgn(_r) ppg trigger input adtg(_r) ad converter trigger frckn(_r) free running timer external clock inn(_r) input capture v il v ih t inh v il v ih t inl external pin input www.datasheet.in mb96350 series fme-mb96350 rev 7 71 external bus timing note: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. basic timing (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 25 ? ns t chcl t cyc /2-5 t cyc /2+5 t clch t cyc /2-5 t cyc /2+5 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -20 20 ns t chcbl -20 20 t clcbh -20 20 t clcbl -20 20 eclk ale time t chlh ale, eclk ? -10 10 ns t chll -10 10 t cllh -10 10 t clll -10 10 eclk address valid time t chav a[23:16], eclk ? -15 15 ns t clav -15 15 t cladv ad[15:0], eclk ? -15 15 ns t chadv -15 15 eclk rdx /wrx time t chrwh rdx, wrx, wrlx,wrhx, eclk ? -10 10 ns t chrwl -10 10 t clrwh -10 10 t clrwl -10 10 www.datasheet.in mb96350 series 72 fme-mb96350 rev 7 (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t cyc eclk ? 30 ? ns t chcl t cyc /2-8 t cyc /2+8 t clch t cyc /2-8 t cyc /2+8 eclk ubx/ lbx / csn time t chcbh csn, ubx, lbx, eclk ? -25 25 ns t chcbl -25 25 t clcbh -25 25 t clcbl -25 25 eclk ale time t chlh ale, eclk ? -15 15 ns t chll -15 15 t cllh -15 15 t clll -15 15 eclk address valid time t chav a[23:16], eclk ? -20 20 ns t clav -20 20 t cladv ad[15:0], eclk ? -20 20 ns t chadv -20 20 eclk rdx /wrx time t chrwh rdx, wrx, wrlx, wrhx, eclk ? -15 15 ns t chrwl -15 15 t clrwh -15 15 t clrwl -15 15 www.datasheet.in mb96350 series fme-mb96350 rev 7 73 eclk t cyc csn ale a[23:16] 0.2*vcc t chcl t chav t chcbl t chcbh lbx ubx t cllh t chll t chlh t clll t cladv ad[15:0] address t clav t chadv t clcbh t clcbl t chrwh t clrwh t clrwl t chrwl rdx wrx (wrlx, wrhx) 0.8*vcc t clch refer to the hardware manual for detailed timing charts www.datasheet.in mb96350 series 74 fme-mb96350 rev 7 bus timing (read) (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 5 ? ns eacl:sts=1 t cyc ? 5 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 5 ? valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 15 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 15 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 15 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 15 ? t advll ale,ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 15 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 15 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 15 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 15 ? ale ? address valid time t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 -15 ? valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? t advrl rdx, ad[15:0] eacl:ace=0 t cyc ? 15 ? ns eacl:ace=1 2t cyc ? 15 ? valid address ? valid data input t avdv a[23:16], ad[15:0] eacl:ace=0 ? 3t cyc ? 55 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 55 t advdv ad[15:0] eacl:ace=0 ? 5t cyc /2 ? 55 ns w/o cycle extension eacl:ace=1 ? 7t cyc /2 ? 55 rdx pulse width t rlrh rdx ? 3 t cyc /2 ? 5 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 50 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns www.datasheet.in mb96350 series fme-mb96350 rev 7 75 address valid ? data hold time t axdx a[23:16], ad[15:0] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 10 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 10 ? valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 15 ? ns t advch ad[15:0], eclk t cyc /2 ? 15 ? rdx ? eclk time t rlch rdx, eclk ? t cyc /2 ? 10 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 10 ? ns eacl:sts=1 ? 10 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 50 ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max ale pulse width t lhll ale eacl:sts=0 and eacl:ace=0 t cyc /2 ? 8 ? ns eacl:sts=1 t cyc ? 8 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 8 ? valid address ? ale time t avll ale, a[23:16], eacl:sts=0 and eacl:ace=0 t cyc ? 20 ? ns eacl:sts=1 and eacl:ace=0 3t cyc /2 ? 20 ? eacl:sts=0 and eacl:ace=1 2t cyc ? 20 ? eacl:sts=1 and eacl:ace=1 5t cyc /2 ? 20 ? t advll ale, ad[15:0] eacl:sts=0 and eacl:ace=0 t cyc /2 ? 20 ? ns eacl:sts=1 and eacl:ace=0 t cyc ? 20 ? eacl:sts=0 and eacl:ace=1 3t cyc /2 ? 20 ? eacl:sts=1 and eacl:ace=1 2t cyc ? 20 ? ale ? address valid time t llax ale, ad[15:0] eacl:sts=0 t cyc /2 ? 20 ? ns eacl:sts=1 -20 ? (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter sym- bol pin conditions value unit remarks min max www.datasheet.in mb96350 series 76 fme-mb96350 rev 7 valid address ? rdx time t avrl rdx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? t advrl rdx, ad[15:0] eacl:ace=0 t cyc ? 20 ? ns eacl:ace=1 2t cyc ? 20 ? valid address ? valid data input t avdv a[23:16], ad[15:0] eacl:ace=0 ? 3t cyc ? 60 ns w/o cycle extension eacl:ace=1 ? 4t cyc ? 60 t advdv ad[15:0] eacl:ace=0 ? 5t cyc /2 ? 60 ns w/o cycle extension eacl:ace=1 ? 7t cyc /2 ? 60 rdx pulse width t rlrh rdx ? 3t cyc /2 ? 8 ? ns w/o cycle extension rdx ? valid data input t rldv rdx, ad[15:0] ?? 3t cyc /2 ? 55 ns w/o cycle extension rdx ? data hold time t rhdx rdx, ad[15:0] ? 0 ? ns address valid ? data hold time t axdx a[23:16] ? 0 ? ns rdx ? ale time t rhlh rdx, ale eacl:sts=1 and eacl:ace=1 3t cyc /2 ? 15 ? ns other ecl:sts, eacl:ace setting t cyc /2 ? 15 ? valid address ? eclk time t avch a[23:16], eclk ? t cyc ? 20 ? ns t advch ad[15:0], eclk t cyc /2 ? 20 ? rdx ? eclk time t rlch rdx, eclk ? t cyc /2 ? 15 ? ns ale ? rdx time t llrl ale, rdx eacl:sts=0 t cyc /2 ? 15 ? ns eacl:sts=1 ? 15 ? eclk ? valid data input t chdv ad[15:0], eclk ?? t cyc ? 55 ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive = 5ma, c l = 50pf) parameter sym- bol pin conditions value unit remarks min max www.datasheet.in mb96350 series fme-mb96350 rev 7 77 . bus timing (write) (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 15 ? ns eacl:ace=1 5t cyc /2 ? 15 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 15 ? ns eacl:ace=1 2t cyc ? 15 ? wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 5 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 20 ? ns w/o cycle extension a[23:16] ad[15:0] address v il v ih v ih v il read data t rhdx t rldv t advdv eclk t advch 0.8*vcc t rlch ale t lhll t rhlh 0.2*v cc t llax t advll rdx t llrl t rlrh t advrl t avch t avll t avdv t avrl t chdv t axdx refer to the hardware manual for detailed timing charts www.datasheet.in mb96350 series 78 fme-mb96350 rev 7 wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 15 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] ? t cyc /2 ? 15 ? ns wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 10 ? ns other ebm:ace and eacl:sts setting t cyc ? 10 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 10 ? ns csn ? wrx time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 15 ns eacl:ace=1 ? 5t cyc /2 ? 15 wrx ? csn time t whcsh wrx, wrlx, wrhx, csn ? t cyc /2 ? 15 ? ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max valid address ? wrx time t avwl wrx, wrlx, wrhx, a[23:16] eacl:ace=0 3t cyc /2 ? 20 ? ns eacl:ace=1 5t cyc /2 ? 20 ? t advwl wrx, wrlx, wrhx, ad[15:0] eacl:ace=0 t cyc ? 20 ? ns eacl:ace=1 2t cyc ? 20 ? wrx pulse width t wlwh wrx, wrxl, wrhx ? t cyc ? 8 ? ns w/o cycle extension valid data output ? wrx time t dvwh wrx, wrlx, wrhx, ad[15:0] ? t cyc ? 25 ? ns w/o cycle extension wrx ? data hold time t whdx wrx, wrlx, wrhx, ad[15:0] ? t cyc /2 ? 20 ? ns wrx ? address valid time t whax wrx, wrlx, wrhx, a[23:16] ? t cyc /2 ? 20 ? ns (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max www.datasheet.in mb96350 series fme-mb96350 rev 7 79 . wrx ? ale time t whlh wrx, wrlx, wrhx, ale ebm:ace=1 and eacl:sts=1 2t cyc ? 15 ? ns other ebm:ace and eacl:sts setting t cyc ? 15 ? wrx ? eclk time t wlch wrx, wrlx, wrhx, eclk ? t cyc /2 ? 15 ? ns csn ? wrx time t cslwl wrx, wrlx, wrhx, csn eacl:ace=0 ? 3t cyc /2 ? 20 ns eacl:ace=1 ? 5t cyc /2 ? 20 wrx ? csn time t whcsh wrx, wrlx, wrhx, csn ? t cyc /2 ? 20 ? ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value unit remarks min max eclk t wlch 0.8*v cc ale t whlh wrx (wrlx, wrhx) t wlwh t advwl a[23:16] t whax ad[15:0] address write data t dvwh t whdx csn t whcsh t avwl t cslwl 0.2*v cc refer to the hardware manual for detailed timing charts www.datasheet.in mb96350 series 80 fme-mb96350 rev 7 ready input timing note : if the rdy setup time is insuf?ient, use the auto-ready function. hold timing (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 35 ? ns rdy hold time t ryhh rdy 0 ? ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin test condition rated value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns (t a =? 40 cto + 125 c, v cc = 5.0 v 10 % ,v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 20 t cyc + 20 ns hakx time ? pin valid time t hahv hakx t cyc ? 20 t cyc +20 ns (t a =? 40 cto + 125 c, v cc = 3.0 to 4.5v, v ss = 0.0 v, io drive =5ma,c l = 50pf) parameter symbol pin condition value units remarks min max pin floating ? hakx time t xhal hakx ? t cyc ? 25 t cyc +25 ns hakx time ? pin valid time t hahv hakx t cyc ? 25 t cyc +25 ns eclk rdy when wait is not used. v ih v ih t ryhh rdy when wait is used. t ryhs v il 0.8*v cc refer to the hardware manual for detailed timing charts www.datasheet.in mb96350 series fme-mb96350 rev 7 81 hakx each pin high-z t hahv t xhal 0.8*v cc 0.2*v cc 0.8*v cc 0.2*v cc refer to the hardware manual for detailed timing charts www.datasheet.in mb96350 series 82 fme-mb96350 rev 7 usart timing warning: the values given below are for an i/o driving strength io drive = 5ma. if io drive is 2ma, all the maximum output timing described in the different tables must then be increased by 10ns. notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in ?b96300 super series hardware manual ? t clkp1 is the cycle time of the peripheral clock 1 (clkp1), unit : ns *1: parameter n depends on t scyci and can be calculated as follows: if t scyci = 2*k*t clkp1 , then n = k, where k is an integer > 2 if t scyci = (2*k+1)*t clkp1 , then n = k+1, where k is an integer > 1 examples: (t a = -40?c to 125?c, v cc = 3.0v to 5.5v, v ss = av ss = 0v, io drive = 5ma, c l = 50pf) parameter symbol pin condition v cc =av cc = 4.5v to 5.5v v cc =av cc = 3.0v to 4.5v unit min max min max serial clock cycle time t scyci sckn internal shift clock mode 4 t clkp1 ? 4 t clkp1 ? ns sck sot delay time t slovi sckn, sotn -20 + 20 -30 + 30 ns sot sck delay time t ovshi sckn, sotn n*t clkp1 - 20 *1 ? n*t clkp1 - 30 *1 ? ns valid sin sck t ivshi sckn, sinn t clkp1 + 45 ? t clkp1 + 55 ? ns sck valid sin hold time t shixi sckn, sinn 0 ? 0 ? ns serial clock ??pulse width t slshe sckn external shift clock mode t clkp1 + 10 ? t clkp1 + 10 ? ns serial clock ??pulse width t shsle sckn t clkp1 + 10 ? t clkp1 + 10 ? ns sck sot delay time t slove sckn, sotn ? 2 t clkp1 + 45 ? 2 t clkp1 + 55 ns valid sin sck t ivshe sckn, sinn t clkp1 /2 + 10 ? t clkp1 /2 + 10 ? ns sck valid sin hold time t shixe sckn, sinn t clkp1 + 10 ? t clkp1 + 10 ? ns sck fall time t fe sckn ? 20 ? 20 ns sck rise time t re sckn ? 20 ? 20 ns t scyci n 4*t clkp1 2 5*t clkp1, 6*t clkp1 3 7*t clkp1, 8*t clkp1 4 ... ... www.datasheet.in mb96350 series fme-mb96350 rev 7 83 internal shift clock mode sot t slovi sin v il v ih t ivshi v il v ih t shixi t ovshi sck for escr:sces = 0 0.8*v cc t scyci sck for escr:sces = 1 0.8*v cc 0.8*v cc 0.2*v cc 0.2*v cc 0.2*v cc 0.8*v cc 0.2*v cc external shift clock mode t fe v il v il v il v il sot t slove sin v il v ih t ivshe v il v ih t shixe v ih t re v ih t slshe v il v ih t shsle v ih v ih sck for escr:sces = 0 sck for escr:sces = 1 0.8*v cc 0.2*v cc www.datasheet.in mb96350 series 84 fme-mb96350 rev 7 i 2 c timing *1 : for use at over 100 khz, set the peripheral clock 1 to at least 6 mhz. *2 : c b = capacitance of one bus line in pf. *3 : t clkp1 is the cycle time of the periperal clock clkp1. ? oh = 0.7 * v cc ? ol = 0.3 * v cc cmos hysteresis 0.7/0.3 input selected (t a = -40?c to 125?c, v cc = av cc = 3.0v to 5.5v,v ss = av ss =0v) parameter symbol standard-mode fast-mode* 1 unit min max min max scl clock frequency f scl 0 100 0 400 khz hold time (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ??width of the scl clock t low 4.7 ? 1.3 ? s ??width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45 0 0.9 s data set-up time sda scl t sudat 250 ? 100 ? ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between a stop and start condition t bus 4.7 ? 1.3 ? s output fall time from 0.7*vcc to 0.3*vcc with a bus capacitance from 10 pf to 400 pf t of 20 + 0.1*c b * 2 250 20 + 0.1*c b * 2 250 ns capacitive load for each bus line c b ? 400 ? 400 pf pulse width of spikes which will be sup- pressed by input noise filter t sp n/a n/a 0 1*t clkp1 * 3 ns sda scl t low t sudat t hdsta t bus t hdsta t hddat t high t susta t susto www.datasheet.in mb96350 series fme-mb96350 rev 7 85 5. analog digital converter note: the accuracy gets worse as |avrh - avrl| becomes smaller. (t a = -40 ?c to +125 ?c, 3.0 v avrh - avrl, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter symbol pin value unit remarks min typ max resolution - - - - 10 bit total error - - - - 3 lsb nonlinearity error - - - - 2.5 lsb differential nonlinearity error -- - - 1.9 lsb zero transition voltage v ot ann avrl - 1.5 lsb avrl+ 0.5 lsb avrl + 2.5 lsb v full scale transition voltage v fst ann avrh - 3.5 lsb avrh - 1.5 lsb avrh + 0.5 lsb v compare time - - 1.0 - 16,500 s 4.5v v cc 5.5v 2.0 - - s 3.0v v cc < 4.5v sampling time - - 0.5 - - s 4.5v v cc 5.5v 1.2 - - s 3.0v v cc < 4.5v analog input leakage current (during conver- sion) i ain ann -1 - +1 a t a 105 ?c, av ss , avrl < v i < av cc , avrh -1.2 - +1.2 a 105 ?c < t a 125 ?c, av ss , avrl < v i < av cc , avrh analog input voltage range v ain ann avrl - avrh v reference voltage range avrh avrh 0.75 avcc - avcc v avrl avrl av ss - 0.25 av cc v power supply current i a avcc - 2.5 5 ma a/d converter active i ah avcc - - 5 a a/d converter not op- erated reference voltage cur- rent i r avrh/ avrl - 0.7 1 ma a/d converter active i rh avrh/ avrl --5 a a/d converter not op- erated offset between input channels - ann - - 4 lsb www.datasheet.in mb96350 series 86 fme-mb96350 rev 7 definition of a/d converter terms resolution: analog variation that is recognized by an a/d converter. t otal error : difference between the actual value and the ideal value. the total error includes zero transition error, full-scale transition error and nonlinearity error. nonlinear ity error : deviation between a line across zero-transition line (?0 0000 0000 <--> ?0 0000 0001? and full-scale transition line (?1 1111 1110?<--> ?1 1111 1111? and actual conversion characteristics. diff erential nonlinear ity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value. zero reading v oltage: input voltage which results in the minimum conversion value. full scale reading v oltage: input voltage which results in the maximum conversion value. 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actually-measured value) actual conversion characteristics ideal characteristics digital output analog input total error of digital output ? = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avrh ? avrl 1024 [v] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh ? 1.5 lsb [v] v nt : a voltage at which digital output transitions from (n ? 1) to n. total error n: a/d converter digital output value www.datasheet.in mb96350 series fme-mb96350 rev 7 87 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) nonlinearity error differential nonlinearity error differential nonlinearity error of digital output n = 1 lsb = nonlinearity error of digital output n = v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] n : a/d converter digital output value v ot : voltage at which digital output transits from ?00 h ?to ?01 h . v fst : voltage at which digital output transits from ?fe h ?to ?ff h . www.datasheet.in mb96350 series 88 fme-mb96350 rev 7 accuracy and setting of the a/d converter sampling time if the external impedance is too high or the sampling time too short, the analog voltage charged to the internal sample and hold capacitor is insuf?ient, adversely affecting the a/d conversion precision. to satisfy the a/d conversion precision, a suf?ient sampling time must be selected. the required sampling time depends on the external driving impedance r ext , the board capacitance of the a/d converter input pin c ext and the av cc voltage level. the following replacement model can be used for the calculation: the sampling time should be set to minimum ? ? the following approximation formula for the replacement model above can be used: t samp [min] = 7 (r ext (c ext + c in ) + (r ext + r adc ) c adc ) do not select a sampling time below the absolute minimum permitted value (0.5 s for 4.5v av cc 5.5v; 1.2 s for 3.0v av cc < 4.5v). if the sampling time cannot be suf?ient, connect a capacitor of about 0.1 f to the analog input pin. in this case the internal sampling capacitance c adc will be charged out of this external capacitance. a big external driving impedance also adversely affects the a/d conversion precision due to the pin input leakage current i il (static current before the sampling switch) or the analog input leakage current i ain (total leakage current of pin input and comparator during sampling). the effect of the pin input leakage current i il cannot be compensated by an external capacitor. the accuracy gets worse as |avrh - avrl| becomes smaller. comparator sampling switch r adc c adc analog r ext c ext input mcu source r ext : external driving impedance c ext : capacitance of pcb at a/d converter input r adc : resistance within mcu: 2.6k ? (max) for 4.5v av cc 5.5v 12k ? (max) for 3.0v av cc < 4.5v c adc : sampling capacitance within mcu: 10pf (max) c in c in : capacitance of mcu input pin: 15pf (max) www.datasheet.in mb96350 series fme-mb96350 rev 7 89 6. low voltage detector characteristics *1: valid for all devices except devices listed under ?2 *2: valid for: MB96F353/f355 cilcr:lvl[3:0] are the low voltage detector level select bits of the cilcr register. for correct detection, the slope of the voltage level must satisfy . faster variations are regarded as noise and may not be detected. the functional operation of the mcu is guaranteed down to the minimum low voltage detection level of ?evel 0 (v dl0_min ). the electrical characteristics however are only valid in the speci?d range (usually down to 3.0v). (t a = -40 ?c to +125 ?c, v cc = av cc = 3.0v - 5.5v, v ss = av ss = 0v) parameter symbol value *1 value *2 unit remarks min max min max stabilization time t lvdstab - 75 - 110 s after power-up or change of detection level level 0 v dl0 2.7 2.9 2.5 2.9 v cilcr:lvl[3:0]=?000 level 1 v dl1 2.9 3.1 2.8 3.2 v cilcr:lvl[3:0]=?001 level 2 v dl2 3.1 3.3 3 3.4 v cilcr:lvl[3:0]=?010 level 3 v dl3 3.5 3.75 3.35 3.8 v cilcr:lvl[3:0]=?011 level 4 v dl4 3.6 3.85 3.5 3.95 v cilcr:lvl[3:0]=?100 level 5 v dl5 3.7 3.95 3.6 4.1 v cilcr:lvl[3:0]=?101 level 6 v dl6 3.8 4.05 3.7 4.2 v cilcr:lvl[3:0]=?110 level 7 v dl7 3.9 4.15 3.8 4.3 v cilcr:lvl[3:0]=?111 level 8 v dl8 4.0 4.25 3.9 4.4 v cilcr:lvl[3:0]=?000 level 9 v dl9 4.1 4.35 3.95 4.5 v cilcr:lvl[3:0]=?001 level 10 v dl10 not used not used level 11 v dl11 not used not used level 12 v dl12 not used 2.6 3 v cilcr:lvl[3:0]=?100 level 13 v dl13 not used not used level 14 v dl14 not used not used level 15 v dl15 not used not used t d d v 0.004 v s ----- www.datasheet.in mb96350 series 90 fme-mb96350 rev 7 low voltage detector operation in the following ?ure, the occurrence of a low voltage condition is illustrated. for a detailed description of the reset and startup behavior, please refer to the corresponding hardware manual chapter. voltage [v] time [s] v cc v dlx, min v dlx, max dv dt low voltage reset assertion normal operation power reset extension time www.datasheet.in mb96350 series fme-mb96350 rev 7 91 7. flash memory program/erase characteristics *1: this value was converted from the results of evaluating the reliability of the technology (using arrhenius equation to convert high temperature measurements into normalized value at 85 o c) (t a = -40?c to 105?c, v cc = av cc = 3.0v to 5.5v, v ss = av ss = 0v) parameter value unit remarks min typ max sector erase time - 0.9 3.6 s without erasure pre-program- ming time chip erase time - n*0.9 n*3.6 s without erasure pre-program- ming time (n is the number of flash sector of the device) word (16-bit width) programming time - 23 370 us without overhead time for sub- mitting write command program/erase cycle 10 000 - - cycle flash data retention time 20 - - year *1 www.datasheet.in mb96350 series 92 fme-mb96350 rev 7 example characteristics 1. temperature dependency of power supply currents the following diagrams show the current consumption of samples with typical wafer process parameters in differ- ent operation modes. common condition for all operation modes: ? cc = av cc = 5.0v main clock = 4mhz external clock sub clock = 32khz external clock operation mode details: mode name details pll run 56 pll run mode current i ccpll with the following settings: ? clks1 = f clks2 = f clkb = f clkp1 = 56mhz ? clkp2 = 28mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) 2 flash/rom wait states (mtcra=233a h ) rc oscillator and sub oscillator stopped pll run 48 pll run mode current i ccpll with the following settings: ? clks1 = f clks2 = 96mhz ? clkb = f clkp1 = 48mhz ? clkp2 = 24mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) 1 flash/rom wait states (mtcra=6b09 h ) rc oscillator and sub oscillator stopped pll run 24 pll run mode current i ccpll with the following settings: ? clks1 = f clks2 = 48mhz ? clkb = f clkp1 = f clkp2 = 24mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 0 flash/rom wait states (mtcra=2208 h ) rc oscillator and sub oscillator stopped main run main run mode current i ccmain with the following settings: ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 4mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, rc oscillator and sub oscillator stopped www.datasheet.in mb96350 series fme-mb96350 rev 7 93 rc run 2m rc run mode current i ccrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 2mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, main oscillator and sub oscillator stopped rc run 100k rc run mode current i ccrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 100khz regulator in low power mode a (smcr:lpms = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, main oscillator and sub oscillator stopped sub run sub run mode current i ccsub with the following settings: ? clks1 = f clks2 = f clkb = f clkp1 = f clkp2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) 1 flash/rom wait states (mtcra=0239 h ) pll, rc oscillator and main oscillator stopped pll sleep 56 pll sleep mode current i ccspll with the following settings: ? clks1 = f clks2 = f clkp1 = 56mhz ? clkp2 = 28mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) rc oscillator and sub oscillator stopped pll sleep 48 pll sleep mode current i ccspll with the following settings: ? clks1 = f clks2 = 96mhz ? clkp1 = 48mhz ? clkp2 = 24mhz regulator in high power mode core voltage at 1.9v (vrcr:hpm[1:0] = 11 b ) rc oscillator and sub oscillator stopped pll sleep 24 pll sleep mode current i ccspll with the following settings: ? clks1 = f clks2 = 48mhz ? clkp1 = f clkp2 = 24mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) rc oscillator and sub oscillator stopped main sleep main sleep mode current i ccsmain with the following settings: ? clks1 = f clks2 = f clkp1 = f clkp2 = 4mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) pll, rc oscillator and sub oscillator stopped mode name details www.datasheet.in mb96350 series 94 fme-mb96350 rev 7 rc sleep 2m rc sleep mode current i ccsrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = f clkp1 = f clkp2 = 2mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) pll, main oscillator and sub oscillator stopped rc sleep 100k rc sleep mode current i ccsrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = f clkp1 = f clkp2 = 100khz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped sub sleep sub sleep mode current i ccssub with the following settings: ? clks1 = f clks2 = f clkp1 = f clkp2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and main oscillator stopped pll timer 48 pll timer mode current i cctpll with the following settings: ? clks1 = f clks2 = 48mhz regulator in high power mode core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) rc oscillator and sub oscillator stopped main timer main timer mode current i cctmain with the following settings: ? clks1 = f clks2 = 4mhz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and sub oscillator stopped rc timer 2m rc timer mode current i cctrch with the following settings: rc oscillator set to 2mhz (ckfcr:rcfs = 1) ? clks1 = f clks2 = 2mhz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped rc timer 100k rc timer mode current i cctrcl with the following settings: rc oscillator set to 100khz (ckfcr:rcfs = 0) ? clks1 = f clks2 = 100khz regulator in low power mode a (smcr:lpmss = 1) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, main oscillator and sub oscillator stopped sub timer sub timer mode current i cctsub with the following settings: ? clks1 = f clks2 = 32khz regulator in low power mode a (by hardware) core voltage at 1.8v (vrcr:lpma[2:0] = 110 b ) pll, rc oscillator and main oscillator stopped mode name details www.datasheet.in mb96350 series fme-mb96350 rev 7 95 MB96F353/f355 pll run and sleep mode currents stop 1.8v stop mode current i cch with the following settings: regulator in low power mode b (by hardware) core voltage at 1.8v (vrcr:lpmb[2:0] = 110 b ) stop 1.2v stop mode current i cch with the following settings: regulator in low power mode b (by hardware) core voltage at 1.2v (vrcr:lpmb[2:0] = 000 b ) mode name details 0 10 20 30 40 50 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] pll sleep 24 pll sleep 56 pll sleep 48 pll run 24 pll run 56 pll run 48 www.datasheet.in mb96350 series 96 fme-mb96350 rev 7 MB96F353/f355 operation modes with medium currents MB96F353/f355 low power mode currents 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] rc sleep 2m main sleep pll timer 48 rc run 2m main run 0.001 0.01 0.1 1 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] stop 1.2v stop 1.8v rc timer 100k sub timer sub sleep sub run rc sleep 100k rc timer 2m rc run 100k main timer www.datasheet.in mb96350 series fme-mb96350 rev 7 97 mb96f356 pll run and sleep mode currents mb96f356 operation modes with medium currents 0 10 20 30 40 50 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] pll sleep 24 pll sleep 56 pll sleep 48 pll run 24 pll run 56 pll run 48 0 1 2 3 4 5 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] rc sleep 2m main sleep pll timer 48 rc run 2m main run www.datasheet.in mb96350 series 98 fme-mb96350 rev 7 mb96f356 low power mode currents 0.001 0.01 0.1 1 -60 -40 -20 0 20 40 60 80 100 120 ta [?c] icc[ma] stop 1.2v stop 1.8v rc timer 100k sub timer sub sleep sub run rc sleep 100k rc timer 2m rc run 100k main timer www.datasheet.in mb96350 series fme-mb96350 rev 7 99 2. frequency dependency of power supply currents in pll run mode the following diagrams show the current consumption of samples with typical wafer process parameters in pll run mode at different frequencies and flash timing settings. measurement conditions: ? cc = av cc = 5.0v ta = 25?c ? clks1 = f clkb or f clks1 = 2*f clkb as described in diagram ? clks2 = f clks1 ? clkp1 = f clkb ? clkp2 = f clkb /2 core voltage at 1.8v (vrcr:hpm[1:0] = 10 b ) or 1.9v (vrcr:hpm[1:0] = 11 b ) as described in diagram main clock = 4mhz external clock flash memory timing settings: mtcra=2128 h /2208 h (0 flash wait states, f clks1 = 2*f clkb ) mtcra=0239 h /2129 h (1 flash wait state, f clks1 = f clkb ) mtcra=4c09 h /6b09 h (1 flash wait state, f clks1 = 2*f clkb ) mtcra=233a h (2 flash wait states, f clks1 = f clkb ) average flash access rate (number of read accesses to the flash per clkb clock cycle, no buffer hit): 0 flash wait states: 0.5 1 flash wait states: 0.33 2 flash wait states: 0.25 MB96F353/f355 pll run mode currents 0 5 10 15 20 25 30 35 40 45 0 4 8 121620242832364044485256 clkb/clkp1 (mhz) iccpll (ma) 1 flash wait state (clks1=2*clkb, 1.9v) 1 flash wait state (clks1=2*clkb, 1.8v) 0 flash wait states (clks1=2*clkb, 1.8v) 1 flash wait state (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.9v) : specified in "dc characteristics" www.datasheet.in mb96350 series 100 fme-mb96350 rev 7 mb96f356 pll run mode currents 0 5 10 15 20 25 30 35 40 45 0 4 8 121620242832364044485256 clkb/clkp1 (mhz) iccpll (ma) 1 flash wait state (clks1=2*clkb, 1.9v) 1 flash wait state (clks1=2*clkb, 1.8v) 0 flash wait states (clks1=2*clkb, 1.8v) 1 flash wait state (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.8v) 2 flash wait states (clks1=clkb, 1.9v) : specified in "dc characteristics" www.datasheet.in mb96350 series fme-mb96350 rev 7 101 package dimension mb96(f)35x lqfp 64 - m23 please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max code (reference) p-lfqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 fujit s u limited f640 3 4 s -c-1-1 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00 0.10(.472 .004) s q 14.00 0.20(.551 .00 8 ) s q index 0. 3 2 0.05 (.01 3 .002) m 0.1 3 (.005) 0.145 0.055 (.0057 .0022) "a" .059 .004 +.00 8 0.10 +0.20 1.50 0~ 8 ? 0.25(.010) (mo u nting height) 0.50 0.20 (.020 .00 8 ) 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s ?00 3 -200 8 fujit s u microelectronic s limited f640 3 4 s -c-1-2 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. www.datasheet.in mb96350 series 102 fme-mb96350 rev 7 package dimension mb96(f)35x lqfp 64 - m24 please check the latest package dimension at the following url. http://edevice.fujitsu.com/package/en-search/ 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0. 3 2 g code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m24) (fpt-64p-m24) lead no. det a il s of "a" p a rt 0.25(.010) ( s t a nd off) (.004?004) 0.10?.10 (.024?006) 0.60?.15 (.020?00 8 ) 0.50?.20 1.50 +0.20 ?.10 +.00 8 ?004 .059 0 ? ~ 8 ? "a" 0.0 8 (.00 3 ) (.006?002) 0.145?.055 0.0 8 (.00 3 ) m (.00 8 ?002) 0.20?.05 0.50(.020) 12.00?.20(.472?00 8 ) s q 10.00?.10(. 3 94?004) s q index 49 64 33 4 8 17 3 2 16 1 2005 fujit s u limited f640 3 6 s -c-1-1 c (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s ?005-200 8 fujit s u microelectronic s limited f640 3 6 s -c-1-2 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. www.datasheet.in mb96350 series fme-mb96350 rev 7 103 ordering information mcu with can controller part number flash/rom subclock persistent low volt- age reset package MB96F353rsb pmc-gse2 flash a (96kb) no no 64 pins plastic lqfp (fpt-64p-m23) MB96F353rwb pmc-gse2 yes MB96F353rsb pmc1-gse2 no 64 pins plastic lqfp (fpt-64p-m24) MB96F353rwb pmc1-gse2 yes mb96f355rsb pmc-gse2 flash a (160kb) no 64 pins plastic lqfp (fpt-64p-m23) mb96f355rwb pmc-gse2 yes mb96f355rsb pmc1-gse2 no 64 pins plastic lqfp (fpt-64p-m24) mb96f355rwb pmc1-gse2 yes mb96f356ysb pmc-gse2 flash a (288kb) no yes 64 pins plastic lqfp (fpt-64p-m23) mb96f356rsb pmc-gse2 no mb96f356ywb pmc-gse2 yes yes mb96f356rwb pmc-gse2 no mb96f356ysb pmc1-gse2 no yes 64 pins plastic lqfp (fpt-64p-m24) mb96f356rsb pmc1-gse2 no mb96f356ywb pmc1-gse2 yes yes mb96f356rwb pmc1-gse2 no mb96v300brb-es (for evaluation) emulated by ext. ram yes no 416 pin plastic bga (bga-416p-m02) www.datasheet.in mb96350 series 104 fme-mb96350 rev 7 mcu without can controller this datasheet is also valid for the following outdated devices: mb96f356ysa, mb96f356rsa, mb96f356ywa, mb96f356rwa, mb96f356asa, mb96f356awa, MB96F353rsa, MB96F353rwa, mb96f355rsa, mb96f355rwa, MB96F353asa, MB96F353awa, mb96f355asa, mb96f355awa. part number flash/rom subclock persistent low volt- age reset package MB96F353asb pmc-gse2 flash a (96kb) no no 64 pins plastic lqfp (fpt-64p-m23) MB96F353awb pmc-gse2 yes MB96F353asb pmc1-gse2 no 64 pins plastic lqfp (fpt-64p-m24) MB96F353awb pmc1-gse2 yes mb96f355asb pmc-gse2 flash a (160kb) no 64 pins plastic lqfp (fpt-64p-m23) mb96f355awb pmc-gse2 yes mb96f355asb pmc1-gse2 no 64 pins plastic lqfp (fpt-64p-m24) mb96f355awb pmc1-gse2 yes mb96f356asb pmc-gse2 flash a (288kb) no 64 pins plastic lqfp (fpt-64p-m23) mb96f356awb pmc-gse2 yes mb96f356asb pmc1-gse2 no 64 pins plastic lqfp (fpt-64p-m24) mb96f356awb pmc1-gse2 yes www.datasheet.in mb96350 series fme-mb96350 rev 7 105 revision history revision date modi?ation prelim 1 2007-05-03 creation prelim 2 2007-05-25 electrical characteristics update prelim 3 2007-11-27 package description is removed from cover page. typos corrections in product lineup. product option details added electrical characteristics update update of the block diagram update of the io map pin circuit type, lvd characteristics and example characteristics chapters added prelim 4 2007-12-20 update of the block diagram: external bus address lines, clock output function pins, avrl removed from adc block, relayout. ramstart value is corrected io map regenerated memory map and flash con?uration reworked few typos corrected accross the document. flash bank renaming. ordering information: package type corrected. io circuit drawings modi?d. prelim 5 2008-02-04 reload timer rlt 6 for ppgs added block diagram corrected: icu2 deleted, ttg2,3 deleted, ttg8,9 added pin function description corrected with all existing pin types i/o circuit type diagrams corrected memory map cleaned up "flash sector con?uration" replaced by corrected "user rom memory map for flash devices" parallel flash programming spec removed io map table regenerated: - port register: naming style corrected - memory control registers renamed (main -> a) - addresses after 000bffh removed handling devices: ad converter items added absolute maximum ratings: pd and ta speci?d more precisely run and sleep mode currents: more conditions added (1ws settings) run mode current spec in 48/24mhz mode corrected maximum clks1 frequency corrected at 1.8v external bus timings: missing conditions added and readability improved ordering information updated typos and formatting corrected www.datasheet.in mb96350 series 106 fme-mb96350 rev 7 6 2009-01-09 format adjusted to of?ial fujitsu microelectronics datasheet standard (mainly style changes and of?ial notes and disclaimer added) numbering of electrical characteristics subchapters automated canless devices added (mb96f356a) i/o map: added node about reserved registers serial programming interface: note about handshaking pins improved speci?d ad converter channel offset to 4lsb package code of mb96v300 corrected in ordering information added voltage condition to pull-up resistance spec ordering information: column ?lash/rom added, column ?emarks re- moved of?ial package dimension drawing with additional notes added empty pages removed handling devices: notes added about serial communication and about us- ing ceramic resonators. feature list and ac characteristics: 16mhz maximum frequency is valid for crystal oscillators. for resonators, maximum frequency depends on q-factor ac characteristics: pll phase skew spec added, clkvco min=64mhz vol3 spec improved: spec valid for 3ma load for full vcc range MB96F353/f355 added (under development) free running timer (i/o timer) 2 and 3 added (without clock input pin) input capture icu9 and icu10 added (without input pin, only for lin usart) c-pin cap spec updated: 4.7uf-10uf capacitor with tolerance permitted ?reliminary?watermark removed revision date modi?ation www.datasheet.in mb96350 series fme-mb96350 rev 7 107 7 2010-06-24 ad converter i ain spec improved: 1ua valid up to 105deg, 1.2ua above 105deg low voltage detector: detection levels of MB96F353/f355 updated note added that pll phase jitter spec does not include jitter coming from main clock note added in dc characteristics how to select driving strength of ports i2c ac spec updated: tof, cb and tsp spec added, wrong footnotes and condition removed i/o circuit type: note added for type ? (slew rate control according to i2c spec) example characteristics updated, new ?ures added showing dependency of pll run mode current on frequency updated power supply current spec in run/sleep/timer/stop modes (new spec items in pll run/sleep mode, small adjustment of most other values) package dimension: added the following sentence under the ?ure: ?lease con?m the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ ad converter: impact of input pin capacitance and external capacitance added to formula for calculation of the sampling time added speci?ation of rc clock stabilization time ordering information updated: MB96F353/f355**a -> MB96F353/f355**b, the device development is ?ished feature description i2c: ?-bit addressing?corrected to ?-bit addressing feature description ppg: ?eload timer over?w as clock input corrected to ?eload timer under?w as clock input icclvd speci?ation updated, at 125deg typical value is 7ua and maximum value is 20ua company name updated on the cover page: fujitsu microelectronics limited -> fujitsu semiconductor limited revision date modi?ation www.datasheet.in mb96350 series fme-mb96350 rev 7 www.datasheet.in mb96350 series fme-mb96350 rev 7 109 www.datasheet.in mb96350 series 110 fme-mb96350 rev 7 fujitsu semiconductor limited nomura fudosan shin-yokohama bldg. 10-23, shin-yokohama 2-chome, kohoku-ku yokohama kanagawa 222-0033, japan tel: +81-45-415-5858 http://jp.fujitsu.com/fsl/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower building, 1002 daechi-dong, gangnam-gu, seoul 135-280, republic of korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://kr.fujitsu.com/fmk/ asia paci? fujitsu microelectronics asia pte. ltd. 151 lorong chuan, #05-08 new tech park 556741 singapore tel : +65-6281-0770 fax : +65-6281-0220 http://www.fmal.fujitsu.com/ fujitsu microelectronics shanghai co., ltd. rm. 3102, bund center, no.222 yan an road (e), shanghai 200002, china tel : +86-21-6146-3688 fax : +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road, tsimshatsui, kowloon, hong kong tel : +852-2377-0226 fax : +852-2376-3269 http://cn.fujitsu.com/fmc/en/ specifications are subject to change without notice. for further information please contact each office. all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu semiconductor does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu semiconductor assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu semiconductor or any third party or does fujitsu semiconductor warrant non-infringement of any third-party's intellectual property right or other right by using such information. fujitsu semiconductor assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). please note that fujitsu semiconductor will not be liable against you and/or any third party for any claims or damages aris- ing in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over- current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulations of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited: sales promotion department www.datasheet.in |
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